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28 silicon design engineer jobs at 8 companies in Los Angeles, CA

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Physical Design Engineer II (Silicon Engineering)
Bastrop or Irvine or Sunnyvale
$155k-$185k/yr OnsiteFull Time
SpaceX
SpaceX: Designs and launches advanced rockets and satellite internet constellations.
3+ YOEBachelors in engineering; 3+ years RTL-to-GDSII physical design or flow development.
EDA tools, RTL-to-GDSII, Scripting (Python, TCL, Bash)
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1mo
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Sr. Principal Design Engineer CMOS
Manhattan Beach, California, United States
$142k-$213k/yr OnsiteFull Time
Northrop Grumman
Northrop GrummanNYSE: NOC: Designs and manufactures advanced aerospace and defense systems.
4+ YOEDegree in electrical engineering with 4–9+ years CMOS RF/mixed-signal transistor-level design experience; proficiency with SPICE and Cadence; leadership in silicon bring-up, verification, and lab characterization; security clearance preferred.
SPICE, Cadence
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Analog and Mixed Signal Design Engineer
Pasadena, California, United States
$120k-$160k/yr OnsiteFull Time
AMETEK
AMETEKNYSE: AME: Manufacturer of electronic instruments and electromechanical devices.
2+ YOERequires a B.S. in Electrical Engineering and 2+ years of analog/mixed-signal design experience. Expertise in transistor-level IC design, EDA tools, ADCs, noise analysis, tapeout, and silicon bring-up.
Cadence, Siemens, Synopsys, AI
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2mo
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Senior Staff Digital Design Engineer
Irvine, California, United States
$136k-$201k/yr OnsiteFull Time
Marvell
MarvellNASDAQ: MRVL: Designs and develops high-performance semiconductor and infrastructure solutions.
Bachelor's degree in EE/CE/CS, RTL development with Verilog/SystemVerilog, synthesis/timing/CDC/low-power checks, debug via simulation/emulation/FPGA/silicon, verification/UVM preferred, mentoring and sub-circuit ownership experience.
Verilog, SystemVerilog, UVM, FPGA
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2w
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Principal Design Validation & Test (DVT) Engineer
Irvine, California, United States
OnsiteFull Time
Celero Communications
Celero Communications: Developing high-performance coherent DSP technology for AI connectivity.
8+ YOE8+ years post-silicon validation/DVT experience with complex ASICs/SoCs; Bachelor's in EE/CE/CS or related; Python skills; lab equipment and high-speed protocol expertise; strong debug and communication skills.
JTAG, Python, oscilloscopes, BERTs, protocol analyzers, network analyzers, logic analyzers, Ethernet traffic generators, power measurement equipment, PCIe, Ethernet, SerDes, CXL, SPI, I²C, MDIO, RTL
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3mo
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Electrical/Optical SerDes Analog Mixed Signal Design Engineer
Irvine, California, United States
$150k-$301k/yr OnsiteFull Time
MediaTek
MediaTekTaiwan Stock Exchange: 2454: Designs and develops system-on-chip solutions for electronic devices.
3+ YOEMS or above in EE/Applied Physics, 3+ years experience preferred, expertise in high-speed analog/mixed-signal and silicon photonics, Cadence, MATLAB/Python proficiency, RN-level independent technical ownership and collaboration skills.
Verilog-A, MATLAB, Python, Cadence, Verilog-AMS, Lumerical (INTERCONNECT/FDTD/MODE)
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Senior Staff Engineer, Analog Mixed Signal Design
Irvine or Livonia
$146k-$201k/yr OnsiteFull Time
Infineon Technologies
Infineon TechnologiesFrankfurt Stock Exchange: IFX: Designs and manufactures semiconductors for power and IoT systems.
2+ YOEPhD with 2–4 years or MS (EE) with 3–5 years; strong analog/linear circuit and high-speed design skills; experience with ADC/DAC, amplifiers, PLLs, FinFET nodes, silicon bring-up, and cross-functional communication.
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Sr. Signal & Power Integrity Engineer, Annapurna Labs - AI Silicon Packaging
Cupertino or Austin or Los Angeles County
$183k-$248k/yr OnsiteFull Time
Amazon
AmazonNASDAQ: AMZN: Global online retail and cloud computing technology provider.
10+ YOEBachelor's degree in electrical engineering or related field, 10+ years of signal integrity, power integrity, and package design experience, advanced packaging expertise, and hands-on SI/PI and EM simulation tools experience.
Ansys RedHawk-SC 3DIC, Cadence Voltus, HFSS, Cadence Sigrity, PowerSI, PowerDC, Clarity, ADS, TDR, VNA, oscilloscope, PCIe, UCIe, SerDes, EMIB, CoWoS
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