53 silicon jobs at 12 companies in Los Angeles, CA
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Silicon Validation Engineer
Los Angeles or San Francisco Bay Area
OnsiteFull Time
Bachelor’s degree; experience with high-speed SerDes, CTLE/DFE/PLL; lab characterization; Python programming; knowledge of USB, PCIe, DP protocols.
High-Speed Oscilloscope, BERT, Python, SerDes, CTLE, DFE, FFE, CDR, PLL
2w
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Spring 2027 Silicon Engineering Internship/Co-op
Irvine or Palo Alto or Redmond or Bastrop or Cape Canaveral or Hawthorne or McGregor or Brownsville or Memphis
$30-$40/hr OnsiteInternship
0.25+ YOEMust be enrolled in a bachelor's or graduate program, 3+ months software/hardware/chip experience, U.S. eligibility per ITAR, able to work onsite full time for ≥12 weeks starting Jan or Mar 2027.
C/C++, Verilog, VHDL, Python, Perl, Spice, Timing, Synthesis, Ansys, COMSOL
1d
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Strategic Silicon & Tech Sourcing Principal, Networking Silicon
Cupertino or Seattle or Los Angeles County
$176k-$262k/yr OnsiteFull Time
6+ YOERequires a bachelor's degree, 6+ years developing technology roadmaps and sourcing strategies, 6+ years executive stakeholder experience, and expertise in semiconductor technology, supply chains, negotiations, and cost modeling.
Switch ASIC, AWS, Cloud Computing, Compute, Edge, Hybrid, Security, Networking, End User Compute (EUC), Supply Chain, Contact Center as a Service, Consumer Data Applications, Encrypted Communications, Communication Developer Services, Accelerated Compute, High Performance Compute, Visual/Spatial Compute, IoT, Mainframe, Serverless, Containers, Cloud Operations, AI/ML, GenAI, Analytics, Database, Storage
2mo
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Sr Principal Program Manager
Santa Clara or Westlake Village
$158k-$237k/yr OnsiteFull Time
8+ YOELead end-to-end program management for complex optical and silicon subsystems; cross-functional leadership; strong risk management; 8+ years PM in semiconductors; Bachelor in CS/EE; excellent communication.
5d
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Analog and Mixed Signal Design Engineer
Pasadena, California, United States
$120k-$160k/yr OnsiteFull Time
2+ YOERequires a B.S. in Electrical Engineering and 2+ years of analog/mixed-signal design experience. Expertise in transistor-level IC design, EDA tools, ADCs, noise analysis, tapeout, and silicon bring-up.
Cadence, Siemens, Synopsys, AI
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Staff Reliability/FA Engineer (Irvine, CA, US)
Irvine, California, United States
$114k-$220k/yr OnsiteFull Time
8+ YOEBS degree, minimum 8 years' experience (5+ in silicon semiconductor industry), knowledge of IC reliability and JEDEC standards, Python and ML/AI familiarity, Microsoft Office proficiency, strong analytical and communication skills.
Python, Microsoft Excel, Microsoft Word, Microsoft PowerPoint, machine learning, AI, automation tools
2mo
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Lead Principal Engineer Applications - DC/DC switch mode
Andover or El Segundo
$180k-$247k/yr HybridFull Time
3+ YOEExperience in DC/DC switch-mode power supplies, 3+ years in silicon controller product development, hands-on lab debugging, MATLAB/Simulink or SIMetrix experience, ability to support customers and define controller architectures.
MATLAB/Simulink, SIMetrix, digital oscilloscope, function generator, network analyzer
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Principal Design Validation & Test (DVT) Engineer
Irvine, California, United States
OnsiteFull Time
8+ YOE8+ years post-silicon validation/DVT experience with complex ASICs/SoCs; Bachelor's in EE/CE/CS or related; Python skills; lab equipment and high-speed protocol expertise; strong debug and communication skills.
JTAG, Python, oscilloscopes, BERTs, protocol analyzers, network analyzers, logic analyzers, Ethernet traffic generators, power measurement equipment, PCIe, Ethernet, SerDes, CXL, SPI, I²C, MDIO, RTL
1mo
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Sr. Principal Design Engineer CMOS
Manhattan Beach, California, United States
$142k-$213k/yr OnsiteFull Time
4+ YOEDegree in electrical engineering with 4–9+ years CMOS RF/mixed-signal transistor-level design experience; proficiency with SPICE and Cadence; leadership in silicon bring-up, verification, and lab characterization; security clearance preferred.
SPICE, Cadence
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Electrical/Optical SerDes Analog Mixed Signal Design Engineer
Irvine, California, United States
$150k-$301k/yr OnsiteFull Time
3+ YOEMS or above in EE/Applied Physics, 3+ years experience preferred, expertise in high-speed analog/mixed-signal and silicon photonics, Cadence, MATLAB/Python proficiency, RN-level independent technical ownership and collaboration skills.
Verilog-A, MATLAB, Python, Cadence, Verilog-AMS, Lumerical (INTERCONNECT/FDTD/MODE)
2mo
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Analog ATE Test Engineer
Aliso Viejo, California, United States
OnsiteFull Time
5+ YOE5–8+ years analog ATE test engineering experience (8+ with BS EE or 5+ with MS), production experience with Advantest V93000 and SmarTest 8, Python and Java programming, post-silicon validation and PCB debugging experience.
Advantest V93000, SmarTest 8, Python, Java
2mo
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Senior Staff Engineer, Analog Mixed Signal Design
Irvine or California
$146k-$201k/yr OnsiteFull Time
3+ YOEPhD (3–5 yrs) or MS EE (5–7 yrs) with strong analog/high-speed design experience in ADC/DAC, amplifiers, PLLs, regulators and FinFET nodes; lab characterization and silicon debug; strong communication.
2mo
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PCS CPO Commercial Technology Manager, US West (California, CA, US)
California or San Francisco or Los Angeles or San Diego or United States
$126k-$174k/yr OnsiteFull Time
10+ YOEMaster's or Doctorate in physics/engineering/applied science, 10+ years in technology or product development in a technical/OEM setting, experience leading cross-functional teams, deep optics/glass/Silicon Photonics expertise, strong customer engagement and communication skills.
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