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Silicon/Electrical Validation Engineer
Hillsboro or Phoenix
$106k-$200k/yr HybridFull Time
3+ YOEBachelor's in electrical engineering (or related) with 3+ years (or Master's with 1+), experience with high-speed CPU I/O circuits, Python or C/C++, hardware lab/test equipment experience, strong analytical and communication skills.
Python, C/C++
1w
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Senior Validation Engineer
Tempe, Arizona, United States
OnsiteFull Time
5+ YOEHands-on post-silicon validation and bring-up of high-speed analog/mixed-signal devices, 5+ years lab experience, proficiency with BERT, oscilloscopes and Python, strong signal integrity and debugging skills; Bachelor's/Master's preferred.
BERT, High Bandwidth Oscilloscope, Signal generator, Compliance S/W, DDR5 Application Software, Python
1mo
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PCIe / CXL and HSIO Validation Engineer
Austin or Santa Clara or Seattle or Phoenix
$143k-$245k/yr HybridFull Time
5+ YOEBSEE (7+ yrs) or MSEE (5+ yrs) with hands-on post-silicon validation of high-speed IO (PCIe, CXL, UCIe); experience with validation infrastructure, board/platform debug, lab equipment, scripting (C/C++, Python, Perl) and Server OSes.
PCIe Gen5/6+, CXL, UCIe, C/C++, Python, Perl, Linux, Windows, protocol/logic analyzers, oscilloscopes
1mo
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Senior Analog Design Engineer
Phoenix or Chandler or Hillsboro
$191k-$269k/yr HybridFull Time
6+ YOEBSc in EE or related, 6+ years analog/mixed-signal design experience for high-speed SerDes or similar, proficiency with Cadence/HSPICE, post-silicon validation, and strong communication and debugging skills.
Cadence Virtuoso/ADE, HSPICE, Cadence, Synopsys, Verilog-A, MATLAB, Python, Tcl
2w
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R&D Engineer Hardware 4
Chandler, Arizona, United States
$110k-$176k/yr OnsiteFull Time
6+ YOEMSEE or PhD preferred, 6+ years industry experience, expertise in mixed-signal/analog IC design, Cadence Virtuoso, SPICE simulators, Verilog, Synopsys Liberty, Python; silicon validation and documentation experience.
Cadence Virtuoso, ADE, Spectre, Hspice, Finesim, Verilog, Synopsys Liberty, Python
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Staff Power IC Design Engineer
Chandler, Arizona, United States
OnsiteFull Time
7+ YOEMSEE (7+ years) or PhD (5+ years) in power IC design, strong transistor-level design skills, tape-out/silicon validation experience, BCD/HV-CMOS knowledge, Cadence Virtuoso/Spectre/APS proficiency, control-loop and stability expertise.
Cadence Virtuoso, Spectre, APS