11 silicon validation engineer jobs at 4 companies in Portland, OR
2mo
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Post-silicon Validation and Debug Engineer
Hillsboro or Folsom
$106k-$200k/yr OnsiteFull Time
2+ YOEBachelor's degree in EE/CE/CS, 2+ years post-silicon validation/pre-silicon verification or design experience, 1+ year with silicon validation lab equipment and scripting (Python, C/C++, Perl); strong debugging, communication, and cross-functional collaboration skills.
Python, C/C++, Perl, Logic analyzer, Oscilloscope
2mo
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Silicon Validation Software Engineer- GPU IP Validation and Integration
Beaverton, Oregon, United States
OnsiteFull Time
Develop graphics validation software and integrate it into system-level test environments for GPU IP and SoC validation; collaborate with cross-disciplinary engineering teams.
3w
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Principal Silicon Engineer
Mountain View or Austin or Hillsboro or Redmond or Raleigh
$143k-$275k/yr HybridFull Time
3+ YOEPhD/MS/BS in EE/CE/CS or related with relevant years of experience, strong PLL and high-speed clocking expertise, post-silicon validation skills, scripting (Python/Perl), Matlab/Simulink knowledge, and ability to pass Microsoft security/export screenings.
Python, Perl, Matlab (Simulink), Analog Behavioural Modeling (ABM)
1w
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Senior Silicon Engineer
Mountain View or Austin or Redmond or Hillsboro or Raleigh
$120k-$235k/yr HybridFull Time
1+ YOEAdvanced degree in EE/CE/CS or equivalent experience with 1–7+ years engineering experience depending on degree; ability to pass Microsoft cloud background and export-control screening; experience with analog SerDes, validation, and timing modeling.
System Verilog, LEC, Python, Perl
2w
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Principal Silicon Engineer - System Modeling
Mountain View or Redmond or Raleigh or Hillsboro or Austin
$143k-$275k/yr HybridFull Time
3+ YOEDoctorate/Master's/Bachelor's with corresponding technical experience; security screening and export-control eligibility required; post-silicon validation, modeling, and analog/SerDes experience preferred.
Matlab (Simulink), Python, Perl, Cadence Spectre, HSPICE
2mo
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Principal Silicon Design Verification Engineer
Santa Clara or Mountain View or Hillsboro or Austin or Boise or San Diego or Redmond
$143k-$275k/yr HybridFull Time
3+ YOEValidate PCIe IP using UVM testbenches, develop test plans, manage regressions, and meet coverage goals. Requires relevant degree plus 3–8+ years of technical engineering experience and ability to pass Microsoft security screening.
Verilog, System Verilog, UVM, UVM/C, PCIe, NVMe, RDMA, SoC
2w
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SoC HW (Digital, Analog or PnP) Validation Engineer
Hillsboro, Oregon, United States
$102k-$202k/yr HybridFull Time
1+ YOEExperience in post-silicon validation, SoC debug, test content and tools development; proficiency with Python or C/C++; degree in EE/CE/CS with 1–2+ years technical engineering experience; ability to pass security/export screening.
Python, C/C++, JTAG, protocol analyzers, bit error rate tester, logic analyzers, oscilloscope, emulation, FPGA
2w
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Principal Applications Engineer (SiPh)
Beaverton, Oregon, United States
$94k-$123k/yr OnsiteFull Time
5+ YOERecognized technical expert in silicon photonics and semiconductor test; 5+ years related experience (with bachelor) or equivalent advanced degree; customer-facing applications engineering and test validation experience.
1w
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Senior Design Verification Engineer
Mountain View or Redmond or Hillsboro
$120k-$235k/yr HybridFull Time
Experience creating verification environments, pre-/post-silicon validation, strong knowledge of verification methodologies and languages, and ability to pass security/export screenings.
Verilog, VHDL, System Verilog, UVM, C/C++, Python, Ruby, Perl, Makefiles, FPGA
2mo
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Senior Firmware Development Engineer
Mountain View or Redmond or Hillsboro
$120k-$235k/yr HybridFull Time
5+ YOEDegree in EE/CE/CS or equivalent experience; significant firmware/embedded or post-silicon validation experience; proficiency in C++ and hardware technologies (PCIe, memory); ability to pass Microsoft security screening.
C++, PCIe, DMAs, DDR, HBM, CMake, CI/CD, NCCL, Mistral, CUDA, GPU, MAIA, TDP, PVT
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Senior Analog Design Engineer
Phoenix or Chandler or Hillsboro
$191k-$269k/yr HybridFull Time
6+ YOEBSc in EE or related, 6+ years analog/mixed-signal design experience for high-speed SerDes or similar, proficiency with Cadence/HSPICE, post-silicon validation, and strong communication and debugging skills.
Cadence Virtuoso/ADE, HSPICE, Cadence, Synopsys, Verilog-A, MATLAB, Python, Tcl