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Sr. Engineer Electrical
Round Rock, Texas, United States
OnsiteFull Time
5+ YOE5–8 years in designing rotating machines; CAD, PDM, and simulation experience; HV equipment knowledge; leadership potential.
CAD, PDM, Simulation software
3w
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Planning Engineer Sr
Taylor or Texas or United States
$109k-$150k/yr OnsiteFull Time
1+ YOEBachelors in electrical engineering or related; 1+ years power system engineering experience (varies by level). Experience with power system simulation (PSSE, VSAT, TSAT, PowerWorld, PSCAD), dynamic stability and EMT analyses, Python preferred, and knowledge of NERC standards.
PSSE, VSAT, TSAT, PowerWorld, PSCAD, Python
1w
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Planning Engineer - Batch Stability Studies
Taylor, Texas, United States
$87k-$120k/yr HybridFull Time
1+ YOEPerform stability assessments and transmission planning studies using power system simulation tools; bachelor’s in electrical engineering or equivalent; 1–8+ years power system engineering experience depending on level.
PSSE, VSAT, TSAT, PowerWorld, Python
1w
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Planning Engineer Lead - Batch Stability Studies
Taylor, Texas, United States
$144k-$198k/yr HybridFull Time
1+ YOE8+ MgmtBachelor's in electrical engineering (or equivalent), power system stability and transmission planning experience, proficiency with power system simulation tools and Python, strong communication and technical analysis skills.
PSSE, VSAT, TSAT, PowerWorld, Python
2w
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Electrical Principal Engineer- FPGA Development
Round Rock, Texas, United States
$145k-$187k/yr OnsiteFull Time
10+ YOE10+ years industry experience with product development from concept to production; advanced PCBA and HDL (Verilog/System Verilog) skills; RTL design and simulation; analog and digital design fundamentals; hardware/software interaction knowledge.
Verilog, System Verilog, HDL, RTL, Lattice, Xilinx, Altera, Synopsys VCS, Python, Batch, Git
1mo
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Senior Principal Electrical Engineer - FPGA Development
Round Rock, Texas, United States
$174k-$226k/yr OnsiteFull Time
12+ YOE12+ years product development experience; advanced FPGA technologies, Verilog/SystemVerilog and HDL coding; RTL design and simulation; strong analog and digital fundamentals; hardware-software integration. Toolchain experience (Lattice/Xilinx/Altera, Synopsys VCS), Python and Git preferred.
Verilog, SystemVerilog, HDL, RTL, Lattice, Xilinx, Altera, Synopsys VCS, Python, Batch, Git