1mo
Save
Mark Applied
Hide
Sr. Simulation Engineer
Clemmons, North Carolina, United States
OnsiteFull Time
5+ YOEBachelor's in Mechanical or Aerospace Engineering (Master's preferred); 5+ years industrial CFD experience with rotating equipment; proficiency with commercial CFD solvers, turbulence modeling, meshing, CHT, multiphase/cavitation, scripting (Python/Java/MATLAB), 3D CAD (SolidWorks/NX/Creo), and CFD-to-test correlation; experience mentoring engineer...
Star-CCM+, Ansys Fluent, CFX, Python, Java, MATLAB, SolidWorks, NX, Creo, AxSTREAM, CFTurbo, BladeGen, TurboDesign, Ansys Mechanical, Abaqus, Adams, Recurdyn, Simpack, Dymola, AMESim, GT-Suite, Flowmaster, OpenFOAM
1mo
Save
Mark Applied
Hide
R&D Senior Engineer
Mebane or Mexico or Germany or Czech Republic
HybridFull Time
8+ YOEBachelors (or Masters preferred) in engineering; 8+ years in electrical power equipment industry (MV reclosers preferred); knowledge of standards and simulation; US work authorization required.
ABB Ability
3mo
Save
Mark Applied
Hide
R&D Electrical Engineer
Pinetops or Mebane
OnsiteFull Time
2+ YOEMaster’s or Bachelor’s in Electrical Engineering with 2+ or 4+ years HV product development; FEM simulations; SolidWorks; 10-15% travel; onsite in NC.
SolidWorks, FEM, CFD, 3D modeling
1w
Save
Mark Applied
Hide
Fall 2026 Co-Op - Digital Design Engineer
Greensboro, North Carolina, United States
HybridInternship
Pursuing MS or PhD in Electrical Engineering or related field; strong DSP knowledge; proficiency in Verilog, Synopsys flows, and Matlab; experience with RTL design, simulation, and verification.
Verilog, Synopsys, Matlab
3mo
Save
Mark Applied
Hide
Analog Design Engineer
Austin or Chandler or Greensboro
HybridFull Time
2+ YOEDesign and develop analog/mixed-signal IC blocks; simulate, verify, and bring-up; collaborate with cross-functional teams.
Matlab, Verilog-A, SystemVerilog, Simulink, Spectre
3mo
Save
Mark Applied
Hide
Senior Analog Design Engineer
Austin or Chandler or Greensboro
HybridFull Time
3+ YOEDesign and verify analog/mixed-signal IC blocks; Architect, simulate, and validate; collaborate across teams from concept to production.
Matlab, Spectre, Verilog-A, SystemVerilog, Simulink
1mo
Save
Mark Applied
Hide
Analog Mixed Signal Modeling Engineer (UL - 02)
Austin or Chandler or Greensboro
HybridFull Time
Master's in EE/Computer Eng required. Experience in mixed-signal product development, analog IC design, SystemVerilog RNM, AMS simulators, verification methodologies, and strong analytical and communication skills.
SystemVerilog Real Number Modeling (SV-RNM), Verilog AMS, AMS simulators, System Verilog Assertions, PSL Assertions, Perforce, GIT, UVM, Simulink, Simscape, Python