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Senior Formal Verification Engineer
Santa Clara or Austin or Westford or Hillsboro
$168k-$311k/yr HybridFull Time
7+ YOE7+ years experience with formal verification, strong knowledge of Verilog/System Verilog, temporal logic assertions, abstraction techniques, scripting in TCL/Perl/Python, and solid understanding of CPU/GPU architectures.
Verilog, System Verilog, temporal logic assertions, TCL, Perl, Python, Jasper Gold, VC Formal, RTL
3mo
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Structural/ Thermal Modeling Engineer 3
Tualatin, Oregon, United States
OnsiteFull Time
PhD in Mechanical Engineering (or related), strong solid mechanics/heat transfer/fluid mechanics background, AI/ML modeling experience, coding ability, and strong communication/teamwork skills.
ABAQUS, ANSYS, NASTRAN, COMSOL, AI/ML, HPC
3mo
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Principal Digital Design Engineer
Chandler or Vancouver or Remote
$200k-$250k/yr HybridFull Time
10+ YOEBachelor's or master's in electrical/computer engineering; 10+ years in digital design with RTL; SoC/subsystem tapeout experience; strong RTL, microarchitecture, back-end flows, DFT/scan, LEC, STA, SDC skills; solid timing, power, and debug expertise.
Synopsys, Cadence, EDA tools, Synthesis, DFT, LEC, STA, SDC, UPF/CPF, RTL