6 v and v engineer jobs at 5 companies in Watsonville, CA
1w
Save
Mark Applied
Hide
Embedded Software V&V Manager
Palo Alto, California, United States
$176k-$317k/yr HybridFull Time
8+ YOE3+ MgmtBachelor's degree in a relevant computer or engineering field, 8+ years in embedded software V&V or SQA, and 3+ years leading technical teams; Python, C/C++, protocols, and SDLC knowledge required.
Python, C, C++, CAN, LIN, Ethernet, SPI, I2C, Jira, Azure DevOps, DOORS, RTOS
1w
Save
Mark Applied
Hide
Manager, IIIV Design and Characterization
Mountain View, California, United States
$192k-$260k/yr OnsiteFull Time
5+ YOERequires 5+ years leading teams and delivering products, plus experience in at least four areas including NPI strategy, III-V design/process, vendor management, qualification, reliability, or validation.
LiDAR, NPI
1mo
Save
Mark Applied
Hide
Staff System Software Integration and Validation Engineer
Palo Alto or Long Beach
HybridFull Time
5+ YOEBachelor's in EE/ME (or equivalent), 5+ years automotive experience, expertise with automotive systems, HIL (dSPACE/Vector VT), CAN/LIN/Ethernet/FlexRay, DBC/LDF/ARXML, test automation, system-level debugging, and V&V planning. Programming experience preferred.
dSPACE, Vector VT, DBC, LDF, ARXML, HIL, CAN, LIN, Ethernet, FlexRay, C, C++, Python, MATLAB
1mo
Save
Mark Applied
Hide
Senior Systems and Network Engineer
San Jose, California, United States
$125k-$160k/yr HybridFull Time
8+ YOE8+ years systems or network engineering experience; Palo Alto Networks firewall administration; enterprise networking, Windows Server, VMware/Proxmox/Hyper-V, Microsoft 365, and Microsoft SQL Server experience; strong documentation and communication skills.
Palo Alto Networks, VMware vSphere/ESXi, Proxmox, Hyper-V, Microsoft 365, Microsoft SQL Server, Windows Server, Cisco
1mo
Save
Mark Applied
Hide
Silicon Design Verification Engineer, Devices and Services
Mountain View, California, United States
$138k-$198k/yr OnsiteFull Time
4+ YOEBachelor's degree or equivalent, 4+ years verification experience, RTL/SystemVerilog/C/C++ verification, EM for ARM/RISC-V IP, familiarity with UVM/SVA/UPF and low-power verification.
SystemVerilog, C, C++, ARM, RISC-V, UVM, SVA, UPF
2w
Save
Mark Applied
Hide
N&V EPM- Noise and Vibration Engineering Program Manager, Acoustics
Cupertino, California, United States
OnsiteFull Time
Drive cross-functional teams to address noise and vibration across product lines, combining deep technical engineering expertise with program management skills.