32 vlsi physical design engineer jobs at 10 companies in United States
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Microprocessor VLSI Physical Design Engineer
Fort Collins, Colorado, United States
HybridFull Time, Full Time
8+ YOEVLSI physical design engineer with strong analytic skills; experience in high-speed design and mentoring.
Verilog, Perl, C, Tcl
2mo
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Senior Software R&D Engineer, VLSI Physical Design
Austin, Texas, United States
$168k-$311k/yr HybridFull Time
6+ YOEBS/MS/PhD in EE or CS (or equivalent), 6+ years VLSI algorithms development in C++, strong VLSI timing optimization knowledge, familiarity with ICC2/Innovus/PrimeTime/Tempus/StarRC and Perl/Tcl/Python, strong communication skills.
C++, C++14, ICC2, Innovus, PrimeTime, Tempus, StarRC, Perl, Tcl, Python, GNNs, reinforcement learning
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Physical Design Engineer
Westford, Massachusetts, United States
$116k-$219k/yr OnsiteFull Time
3+ YOEBSEE/MSEE or equivalent; 3+ years in VLSI physical design on 5nm-3nm; strong P&R, timing, IR drop; scripting in Python/Perl/Tcl; experience with Synopsys and Cadence tools.
Synopsys ICC2, Synopsys DC, Synopsys PT, Synopsys STAR, Synopsys ICV, Cadence Genus, Cadence Innovus, Cadence Tempus, Python, Perl, Tcl, Make
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Physical Design Engineer (PnR / PPA / Timing Closure)
Mountain View, California, United States
$45k-$121k/yr OnsiteFull Time
3+ YOEExperience in physical design (PnR), PPA optimization, timing closure, STA, EMIR analysis, and hardware signoff; 3+ years VLSI physical design experience; degree in electrical/electronics engineering preferred.
Synopsys Fusion Compiler, ICC2, PrimeTime, Cadence Innovus, RedHawk, Voltus
2d
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Advanced Physical Design and Verification Engineer (7036)
San Jose or California
$86k-$134k/yr HybridFull Time
Master’s degree in Electrical Engineering or Computer Science; knowledge of VLSI and physical design; research or internship experience; EDA tools; Python, Perl, or TCL programming; regular customer-site work.
Python, Perl, TCL, EDA, DRC, LVS, ERC, ANTENNA, EMIR, Netlist-GDS, P&R
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Physical Synthesis Implementation Engineer
San Diego, California, United States
$99k-$148k/yr OnsiteFull Time
0+ YOEBachelor's degree in science/engineering, familiarity with Synopsys Design Compiler or Cadence Genus, scripting (TCL, Perl, Python), static timing analysis and VLSI concepts, strong communication; 0–1+ years hardware engineering experience.
Synopsys Design Compiler, Cadence Genus, TCL, Perl, Python
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Lead Engineer
Santa Clara, California, United States
$130k-$140k/yr OnsiteFull Time
8+ YOE8+ years physical design experience, expertise in Synopsys Fusion Compiler, low-power UPF methodologies, PPA optimization, strong Tcl/Python/Shell scripting, B.Tech/M.Tech in ECE/EE/VLSI, excellent communication and leadership.
Synopsys Fusion Compiler, Tcl, Python, Shell, PT, ICV, UPF
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Digital Failure Analysis Engineer (LFAB)
Lehi, Utah, United States
OnsiteFull Time
5+ YOEBachelor's in engineering/physics, 5+ years semiconductor experience, experience with DFT/ATPG and EDA tools preferred, VLSI and digital design knowledge, strong analytical and communication skills.
DFT, ATPG, EDA
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Senior DRAM Product Engineer
Manassas, Virginia, United States
HybridFull Time
3+ YOEBachelor's in EE/CE/Physics/Math (or related) + 3 years' experience; knowledge of semiconductor physics/manufacturing, DRAM operations, VLSI, electrical design/testing, statistical analysis; familiarity with Linux/Unix, JMP, scripting.
Linux, Unix, JMP, Office Software
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Senior DRAM Product Engineer
Manassas, Virginia, United States
HybridFull Time
3+ YOEBachelor's in EE/CE/Physics/Math + 3 years related experience. Requires semiconductor physics/manufacturing and DRAM product operation knowledge, electrical design/testing, VLSI, schematic/layout analysis, statistical analysis, Linux/Unix, JMP, scripting.
Linux, Unix, JMP, Office Software
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Principal Engineer – Multi-Physics Sign-off (Timing, PDN & Thermal)
San Jose or Austin or San Diego
$263k-$355k/yr HybridFull Time
5+ YOEVLSI knowledge with 5+ years system-level experience; hands-on 3DIC/2.5D design and signoff; strong scripting, flow ownership, and cross-team collaboration; familiarity with EDA tool qualification and multiphysics/thermal analysis.
Cadence Integrity 3D-IC, Synopsys 3DIC Compiler, Cadence Celsius Thermal Solver, Ansys Icepak, Ansys RHSC-ET
1d
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Campus-Beginner (149813)
United States
OnsiteFull Time
Formal training or internship in VLSI analog layout design; knowledge of analog and mixed-signal fundamentals, CMOS, fabrication, floorplanning, placement, routing, and physical verification; relevant engineering degree required.
Cadence Virtuoso, Calibre, Assura, PVS, SKILL, Shell
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