NVIDIA
Posted 4mo ago

Senior Design Verification Engineer - GPU Memory Subsystem

NVIDIA
Durham, North Carolina, United States
$136k-$265k/yrOnsiteFull Time
Responsibilities
  • developing strategies
  • performing verification
  • debugging issues
Requirements
  • BS in CompE/EE/CS or equivalent
  • 5+ years pre-silicon ASIC verification experience
  • Knowledge of Verilog/System Verilog
  • UVM and industry-standard tools
  • Strong debugging and programming in Python or C++
Technical tools mentioned
VerilogSystem VerilogUVMPythonC++

Job description

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

 

We're looking for a talented, motivated Senior Design Verification Engineer to join our GPU memory subsystem team in Durham, NC. Looking to join a dynamic team solving complex verification challenges involving caches, coherency, pipelines, and arbitration? This pre-silicon position is perfect for you!

 

What you'll be doing:

  • Actively collaborate with RTL, DV, FV, and Arch teams to then develop and implement design verification strategies for our GPU ASIC memory subsystem IP.

  • Perform functional and performance verification using advanced tools and methodologies. Bring your innovative ideas to the table.

  • Gain a deep understanding of this critical IP's micro-architectural design and implementation while continuing to advance your verification skills.

 

What we need to see:

  • BS Degree in CompE, EE, CS, or equivalent experience

  • 5+ years of experience covering the full scope of pre-silicon ASIC verification, including the development of verification strategy, test plans, tests, testbench components, regression triage, debug, and coverage closure and experience with industry standard tools

  • Working knowledge of computer architecture fundamentals and their constructs in Verilog/System Verilog

 

Ways to stand out from the crowd:

  • Strong analytical thought process and outstanding debug skills.

  • Experience with caches, coherency, complex pipelines, arbiters, or interconnect networks

  • Infrastructure development, use of AI to support design and verification development

  • Testbench development experience, especially with UVM components used in multiple levels of verification

  • Strong programming/scripting experience in Python or C++. Applying suitable algorithms, data structures, and error handling

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until April 24, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

About NVIDIA

Designs graphics processing units and artificial intelligence hardware.

Similar jobs

Design Verification Engineer roles near Durham, North Carolina
2d
Save
Mark Applied
Hide
Design Verification Engineer - DDR Memory Subsystem
Raleigh or Austin or Hillsboro or Mountain View
$102k-$202k/yr HybridFull Time
Microsoft
MicrosoftNASDAQ: MSFT: Develops software, services, devices, and cloud computing solutions.
1+ YOEMaster's degree plus 1+ year or bachelor's degree plus 2+ years in engineering or computer science; experience with hardware verification, UVM, formal verification, simulations, coverage, and technical scripting.
Universal Verification Methodology (UVM), Python, SystemVerilog Test Bench (SVTB), Coherent Hub Interface (CHI), Advanced Microcontroller Bus Architecture (AMBA), PCIe, CXL
2mo
Save
Mark Applied
Hide
Staff Engineer, Design Verification
Morrisville, North Carolina, United States
$115k-$170k/yr OnsiteFull Time
Marvell
MarvellNASDAQ: MRVL: Designs and develops high-performance semiconductor and infrastructure solutions.
12+ YOEExtensive ASIC verification experience leading DV architecture, emulation, post-silicon validation and delivery; strong leadership, communication, and cross-functional skills. Advanced degree plus many years of related experience required.
4mo
Save
Mark Applied
Hide
Design Verification Engineer
Cary or Melbourne or Waltham
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
3+ YOEBachelor's degree; 3+ years experience preferred; strong SystemVerilog/UVM; scalable/test benches; verification tools; scripting (Python/Perl/TCL); PCIe/USB/DDR experience a plus; UPF knowledge a plus; LLM usage a plus.
SystemVerilog, UVM, Python, Perl, TCL, UPF, PCIe, USB, DDR, LLM, waveform viewer, simulators, coverage, gate level simulations, emulation
4mo
Save
Mark Applied
Hide
Senior Design Verification Engineer - GPU Memory Subsystem
Durham, North Carolina, United States
$136k-$265k/yr OnsiteFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
5+ YOEBS in CompE/EE/CS; 5+ years pre-silicon ASIC verification; verification strategy, test plans, tests, regression; Verilog/SystemVerilog knowledge.
Verilog, SystemVerilog, UVM, Python, C++
4mo
Save
Mark Applied
Hide
ASIC design/verification engineer
Durham or United States
$135k-$311k/yr HybridFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Providing global edge-to-cloud infrastructure and IT solutions for businesses.
6+ YOEBachelor’s or Master’s in Electrical/Computer Engineering; 6-10 years in VLSI design/verification; strong knowledge of VLSI, digital logic, and computer architecture; experience with HDL/EDA tools; proficient in English (written and spoken).
Verilog, SystemVerilog, VHDL, EDA, FPGA tools
4mo
Save
Mark Applied
Hide
ASIC design/verification engineer
Durham, North Carolina, United States
$135k-$311k/yr HybridFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Provides global edge-to-cloud technology solutions and IT infrastructure services.
6+ YOEDesign and verify VLSI/ASIC; 6-10 years of experience; Bachelors/Masters in Electrical or Computer Engineering; strong VLSI, EDA, HDL, and programming skills.
HDL, EDA tools, VLSI tools, FPGA tools, Scripting languages
4mo
Save
Mark Applied
Hide
ASIC design/verification engineer
Durham, North Carolina, United States
$135k-$311k/yr HybridFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Provides edge-to-cloud IT infrastructure and platform services.
6+ YOEBachelor’s or Master’s degree in Electrical or Computer Engineering; 6-10 years in VLSI design/verification; strong HDL/EDA skills.
Hardware description language, Electronic design automation, FPGA tools, Programming and scripting
4mo
Save
Mark Applied
Hide
Principal Engineer, Design Verification
Durham, North Carolina, United States
HybridFull Time
Analog Devices
Analog DevicesNASDAQ: ADI: Designs and manufactures semiconductors for signal processing and power management.
10+ YOE3+ Mgmt10+ years SystemVerilog/UVM verification; 3+ years technical leadership; mixed-signal SoCs verification; DV strategy and methodology leadership; strong EDA/tooling expertise.
SystemVerilog, UVM, JasperGold, VC Formal, Python, TCL, Perl, Shell, Portable Stimulus, PSS, AI/ML in verification, Cadence, Synopsys, Mentor, Git, Perforce, Verilog, C/C++, SystemC