3mo
Save
Mark Applied
Hide
Design Verification Engineer
Austin, Texas, United States
OnsiteFull Time
10+ YOEBS with 10+ years in digital verification; SystemVerilog, UVM, Python/Perl; SOC/IP verification experience; strong communication.
SystemVerilog, UVM, Python, Perl, C/C++, Digital design, Scripting
1mo
Save
Mark Applied
Hide
Design Verification Engineer
Lakeway or Austin
OnsiteFull Time
7+ YOEBSc/MSc in engineering or CS, 7+ years verification experience, expert SystemVerilog/UVM development, protocol verification (AXI, DDRx, PCIe, USBx), verification planning, and ability to travel; eligible to work in the US.
SystemVerilog, UVM, Specman/e, C, C++, Python, Perl
4w
Save
Mark Applied
Hide
Design Verification Engineer
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOEBachelor's in EE/electronic engineering or CS required; 12+ years experience; strong System Verilog, UVM/OVM, RTL, C/C++, Perl, SystemC skills; ASIC design verification, debugging, and coverage experience; US work authorization required.
System Verilog, UVM, OVM, RTL, C/C++, Perl, SystemC, Emulators, FPGA
2d
Save
Mark Applied
Hide
ASICS Design Verification Engineer
San Diego, California, United States
$99k-$148k/yr OnsiteFull Time
Bachelor's degree in science or engineering required; experience with architecture/design tools, scripting/programming, and design verification methods preferred; strong communication and documentation skills.
RTL to GDS Flow, Virtuoso
1mo
Save
Mark Applied
Hide
Principal Design Verification Engineer
Austin or Texas or Santa Clara or Malta
$153k-$290k/yr OnsiteFull Time
8+ YOEBachelor's in engineering, 8+ years design verification (CPU/SoC) experience, hands-on SystemVerilog/UVM and constrained-random verification, scripting in Python/Perl/Shell, familiarity with CPU architectures and cache/coherency concepts.
SystemVerilog, UVM, C, Assembly, Python, Perl, Shell
1mo
Save
Mark Applied
Hide
Principal Design Verification Engineer
Austin or Santa Clara
$153k-$290k/yr OnsiteFull Time
8+ YOE8+ years in design verification of CPU/SoC, SystemVerilog/UVM, constrained random verification, and scripting.
SystemVerilog, UVM, Python, Perl, Shell
3mo
Save
Mark Applied
Hide
Design Verification Engineer - SoC
San Jose, California, United States
$150k-$275k/yr OnsiteFull Time
Design verification for ASIC/SoC; SystemVerilog and Python; performance modeling; test benches and verification infrastructure.
SystemVerilog, Python
1mo
Save
Mark Applied
Hide
Design Verification Engineer
Sunnyvale, California, United States
$190k-$230k/yr OnsiteFull Time
3+ YOE3+ years design verification experience; deep knowledge of SystemVerilog, DPI, UVM; strong programming (object-oriented) skills; experience with testbenches, simulation, emulation, and silicon bring-up.
SystemVerilog, DPI, UVM, Python, Perl
3mo
Save
Mark Applied
Hide
Design Verification Engineer
Austin or Chandler or Greensboro
HybridFull Time
0+ YOEBachelor/Master/PhD in Electrical/Computer Engineering or related field; 2+ years with Bachelors; strong HDL/SystemVerilog/UVM; ASIC/silicon verification experience.
Verilog, VHDL, SystemVerilog, UVM
1mo
Save
Mark Applied
Hide
Design Verification Engineer
Santa Clara, California, United States
$146k-$250k/yr OnsiteFull Time
SystemVerilog/UVM verification expertise; IP/subsystem/SoC verification; testbench development; strong debugging and collaboration.
SystemVerilog, UVM, VCS, Verdi/DVE, Python, Shell, Tcl, Make
2d
Save
Mark Applied
Hide
Design Verification Engineer
Mountain View, California, United States
$120k-$475k/yr HybridFull Time
Concept-to-silicon verification experience with SystemVerilog, UVM, ABV, and scripting; production verification and silicon bring-up experience preferred.
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV)
1mo
Save
Mark Applied
Hide
Design Verification Engineer
Boise, Idaho, United States
OnsiteFull Time
Bachelor's in Electrical or Computer Engineering (or equivalent experience); knowledge of CMOS and mixed-signal verification; SystemVerilog, UVM, SVA; experience with HSPICE, VerilogHDL, FINESIM and scripting/Python; strong debugging and communication skills.
SystemVerilog, UVM, SystemVerilog Assertions, HSPICE, VerilogHDL, FINESIM, Python
2d
Save
Mark Applied
Hide
Design Verification Engineer
Raleigh or Hillsboro or Austin or Mountain View or Redmond
$102k-$202k/yr HybridFull Time, Contract
1+ YOEMaster's+1 or Bachelor's+2 years technical engineering experience (or equivalent); verification of silicon/IP using UVM/System Verilog/Formal; Python scripting; knowledge of CHI/AMBA/PCIe/CXL preferred; pass Microsoft Cloud Background Check and export-control screening.
UVM, Formal, System Verilog, Python
1mo
Save
Mark Applied
Hide
Design Verification Engineer
Boise, Idaho, United States
OnsiteFull Time
Bachelor’s degree in Electrical or Computer Engineering; knowledge of digital/analog circuit design, circuit simulation, and semiconductor fundamentals; strong problem-solving and teamwork.
Python, TCL, SPICE, layout tools
1mo
Save
Mark Applied
Hide
Staff Engineer, Design Verification
Santa Clara, California, United States
$114k-$171k/yr OnsiteFull Time
3+ YOEBachelor's in Computer/Electrical Engineering + 3+ years (2+ with MS/PhD); System Verilog/UVM, verification test-plan development, verification tools, C/C++, Python/Perl, and Linux proficiency.
System Verilog/UVM, C/C++, Python, Perl, Linux, CXL, PCIE, Ethernet, ARM
2mo
Save
Mark Applied
Hide
Design Verification Engineer (Data Fabric Verification Engineer)
Austin, Texas, United States
$45k-$121k/yr OnsiteFull Time
3+ YOE3-5 years VLSI/HVL verification experience; strong SystemVerilog and UVM skills; scripting with Perl, Ruby, or Make; familiarity with RTL, formal verification, and tools such as VCS, Cadence, and Mentor Graphics; bachelor's or master's in computer/electrical engineering preferred.
SystemVerilog, UVM, Perl, Ruby, Make, VCS, Cadence, Mentor Graphics
3mo
Save
Mark Applied
Hide
ASIC design/verification engineer
Durham, North Carolina, United States
$135k-$311k/yr HybridFull Time
6+ YOEBachelor’s or Master’s degree in Electrical or Computer Engineering; 6-10 years in VLSI design/verification; strong HDL/EDA skills.
Hardware description language, Electronic design automation, FPGA tools, Programming and scripting
1mo
Save
Mark Applied
Hide
Design Verification Engineer - APS
Dallas, Texas, United States
OnsiteFull Time
8+ YOEBachelor's degree in electrical engineering; 8+ years of experience; strong verification skills and Python, Verilog/SystemVerilog, UVM experience.
UVM, Verilog, SystemVerilog, Python
1mo
Save
Mark Applied
Hide
Senior Design Verification Engineer
Austin, Texas, United States
OnsiteFull Time
4+ YOEBachelor's in EE/CE/CS required, 4+ years IP/SoC design or verification experience, Verilog/SystemVerilog/UVM skills, SVA and verification (test planning, simulation, debug), familiarity with Python, C/C++, Perl, TCL and AI/ML tools; ARM AMBA knowledge a plus.
Verilog, SystemVerilog, UVM, System Verilog Assertion (SVA), Python, C/C++, Perl, TCL, Makefiles, AI/ML tools, ARM AMBA, RTL
3w
Save
Mark Applied
Hide
Design Verification Engineer
Santa Clara, California, United States
$142k-$200k/yr HybridFull Time
3+ YOEBS/MS in EE/CS (3+ years DV), hands-on coding in SystemVerilog, C, C++, Python, experience with UVM/ABV and simulation/formal verification, familiarity with interconnect protocols and AI-assisted development tools.
SystemVerilog, C, C++, Python, UVM, ABV, JasperGold, VC Formal, AI-assisted development tools, emulation, FPGA
Explore Jobs