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United StatesRemote · Hybrid · Onsite · Field · All Environments
United StatesRemote · Hybrid · Onsite · Field · All Environments
United StatesRemote · Hybrid · Onsite · Field · All Environments
United StatesRemote · Hybrid · Onsite · Field · All Environments
1,189 design verification engineer jobs at 311 companies in United States
6d
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Design Verification Engineer
Dallas, Texas, United States
OnsiteFull Time
1+ YOEBachelor's degree in electrical engineering or related field and 1+ year of AMS design verification experience. Preferred: SystemVerilog, UVM, RTL simulation, verification methodologies, and Python, Tcl, or Perl scripting.
SystemVerilog, UVM, Cadence Xcelium, Python, Tcl, Perl
2w
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Design Verification Engineer
Santa Clara or Folsom or Austin
$166k-$250k/yr HybridFull Time
6+ YOEExperienced verification engineer with SystemVerilog, UVM, C/C++, Python or Perl, DDR memory verification, formal verification, and cross-functional hardware, firmware, and software collaboration experience.
SystemVerilog, UVM, C, C++, Python, Perl, DDR5, LPDDR5, LPDDR6, DFI, DIMMs, RTL, BIOS, GLS, NLP, XPROP, VIPs, BFMs
2mo
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Design Verification Engineer
Lakeway or Austin
OnsiteFull Time
7+ YOEBSc/MSc in engineering or CS, 7+ years verification experience, expert SystemVerilog/UVM development, protocol verification (AXI, DDRx, PCIe, USBx), verification planning, and ability to travel; eligible to work in the US.
SystemVerilog, UVM, Specman/e, C, C++, Python, Perl
2mo
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Design Verification Engineer
San Francisco, California, United States
OnsiteFull Time
Digital-focused design verification for pre-silicon IP: DV methodology, test-plan and verification environment development, test writing, debug, coverage, and RTL sign-off for tape-out.
2w
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Design Verification Engineer
San Jose, California, United States
$120k-$200k/yr OnsiteFull Time
5+ YOEBachelor's degree in computer science, computer engineering, or related field; 5+ years' relevant experience; strong SystemVerilog and UVM proficiency; digital design, SoC architecture, verification, scripting, and simulation debugging expertise.
SystemVerilog, UVM, Python, Perl, TCL, shell scripting, Claude
1w
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Design Verification Engineer
Mountain View or California or United States or New York
$102k-$202k/yr HybridFull Time
1+ YOEMaster’s degree and 1+ year, or bachelor’s degree and 2+ years, in engineering or computer science; experience with pre-silicon verification, SystemVerilog, UVM, formal verification, and scripting.
SystemVerilog, UVM, SVA, C, C++, Python, Ruby, Perl, Assembly, Makefiles
1w
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Staff Engineer - Design Verification
Bengaluru or India or San Francisco or Mountain View
RemoteFull Time
8+ YOERequires 8+ years in design verification, a bachelor's or master's degree in electrical or computer engineering, and expertise in SystemVerilog, UVM, SVA, PCIe, CXL, Ethernet, and SoC/IP verification.
SystemVerilog, UVM, C, SVA, PCIe, CXL, Ethernet, UCIe, SoC, AI/ML, DDR, PowerPoint
2mo
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Design Verification Engineer
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOEBachelor's in EE/electronic engineering or CS required; 12+ years experience; strong System Verilog, UVM/OVM, RTL, C/C++, Perl, SystemC skills; ASIC design verification, debugging, and coverage experience; US work authorization required.
System Verilog, UVM, OVM, RTL, C/C++, Perl, SystemC, Emulators, FPGA
5d
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Design Verification Engineer
Rancho Cordova, California, United States
$121k-$194k/yr HybridFull Time
3+ YOEMaster's degree with 3+ years or bachelor's degree with 5+ years in engineering or computer science; pre-silicon memory verification, UVM, SVA, formal verification, mixed-signal simulation, and scripting experience required.
UVM, SystemVerilog Assertions (SVA), Python, Perl, AI-assisted workflows
5d
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SOC Design Verification Engineer
San Diego, California, United States
$99k-$148k/yr OnsiteFull Time
0.5+ YOEBachelor's degree in science, engineering, or a related field required. Master's preferred, with 6+ months of experience in design tools, scripting/programming, and design verification methods.
RTL to GDS Flow, Virtuoso
1w
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Associate Design Verification Engineer
Dallas, Texas, United States
OnsiteFull Time
0+ YOEBachelor's degree in a relevant engineering or computer science field and 0–2 years of digital design verification experience. Requires SystemVerilog, RTL, verification, scripting, protocol, debugging, and collaboration skills.
SystemVerilog, Verilog, Python, Perl, Tcl, I2C, SPI, UART, Universal Verification Methodology (UVM), SystemVerilog Assertions (SVA)
2w
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Staff Design Verification Engineer
Sunnyvale, California, United States
$250k-$300k/yr OnsiteFull Time
10+ YOERequires 10+ years of design verification experience, SystemVerilog, DPI, UVM, Python or Perl, scalable testbench development, verification tools, and strong debugging skills. BS or MS in computer science or electrical engineering desired.
SystemVerilog, DPI, UVM, Python, Perl
1mo
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Design Verification Engineer
Mountain View, California, United States
$120k-$475k/yr HybridFull Time
Concept-to-silicon verification experience; SystemVerilog, Python, C/C++, Bluespec; UVM and assertion-based verification; formal/simulated verification; portable test creation and silicon debug experience.
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV)
1mo
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Senior Design Verification Engineer
Tempe or Independence
$156k-$291k/yr RemoteFull Time
8+ YOE8+ years design verification experience with UVM, SystemVerilog, RTL verification for FPGA/ASIC, Bachelor's in EE/CE, US citizenship, ability to obtain Secret clearance, familiarity with Questa/Xcelium/VCS and AI verification tools.
Universal Verification Methodology (UVM), SystemVerilog, VHDL, Verilog, Questa, Xcelium, VCS, Jira
1mo
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Design Verification Engineer
Aliso Viejo or San Jose or Córdoba or Toronto
OnsiteFull Time
3+ YOEBachelors in EE/CE/CS,3+ years verification experience, SystemVerilog/UVM, coverage-driven verification, C/C++ and scripting (Python,Tcl,Perl),test planning and debug skills.
SystemVerilog, UVM, C, C++, Python, Tcl, Perl
2mo
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Design Verification Engineer
United States
$212k-$246k/yr OnsiteFull Time
10+ YOEBachelor's degree with 10+ years or master's degree with 7+ years; complex ASIC verification experience; SystemVerilog, UVM, C/C++/Python, verification methodologies, coverage, debugging, and cross-functional delivery experience.
SystemVerilog, Universal Verification Methodology (UVM), C, C++, Python, AI/ML
2w
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Sr Design Verification Engineer, HBM Verification Architecture
Richardson, Texas, United States
OnsiteFull Time
4+ YOEBachelor's degree in electrical or computer engineering, 4+ years of verification engineering experience, digital, analog, or mixed-signal verification, and 2+ years in custom or RTL verification flows.
Verilog, FastSpice, Generative AI, AI
1w
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Sr Design Verification Engineer, DRAM
Boise, Idaho, United States
OnsiteFull Time
4+ YOEBachelor’s degree in Electrical Engineering or related field and 4+ years of semiconductor design, verification, or development experience. Requires SPICE, Verilog, circuit modeling, simulation, verification planning, debug, and silicon correlation.
SPICE, Verilog, Synopsys, Cadence Virtuoso, UVM, Python, AI
3w
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Design Verification Engineer- Senior / Principal (200047138)
United States
OnsiteFull Time
The posting provides no qualifications or requirements beyond the Design Verification Engineer role title.
2mo
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Design Verification Engineer
Santa Clara, California, United States
$142k-$200k/yr HybridFull Time
3+ YOEBS/MS in EE/CS (3+ years DV), hands-on coding in SystemVerilog, C, C++, Python, experience with UVM/ABV and simulation/formal verification, familiarity with interconnect protocols and AI-assisted development tools.
SystemVerilog, C, C++, Python, UVM, ABV, JasperGold, VC Formal, AI-assisted development tools, emulation, FPGA
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