31 analog engineer jobs at 12 companies in Superior, AZ
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Power/Analog Engineer
Tempe, Arizona, United States
$95k-$150k/yr OnsiteFull Time
3+ YOE3+ years analog and power converter design experience, familiarity with oscilloscopes/current probes/FRA/multimeters, Bachelor's in Electrical Engineering, U.S. citizenship required, up to 10% domestic travel, ability to obtain Secret clearance.
PSPICE, LTSPICE, HSPICE, Mentor Graphics XxDesigner, ORCAD Capture, Mentor Graphics Expedition, Zuken, oscilloscopes, current probes, frequency response analyzer, multimeters
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Analog Design Engineer
Scottsdale or Chandler or Phoenix
$134k-$168k/yr OnsiteFull Time
10+ YOEBachelor's in Electronic Engineering, 10+ years analog IC design experience, proficiency with Cadence Virtuoso and Mentor Graphics, EM/ESD awareness, bench testing skills, scripting (SKILL/Perl/Python/TCL) a plus, strong communication.
Cadence Virtuoso, Mentor Graphics, SKILL, Perl, Python, TCL
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Sr Staff Analog Engineer
Chandler, Arizona, United States
OnsiteFull Time
8+ YOE8+ years experience in analog/power management IC design, technical leadership, simulation/layout oversight, lab evaluation, mentorship, strong English communication, and ability to travel occasionally internationally.
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Power/Analog Engineer
Tempe, Arizona, United States
$105k-$165k/yr OnsiteFull Time
3+ YOE3+ years in analog and power converter design, Bachelor's in EE, U.S. citizenship required, ability to obtain Secret clearance, familiarity with test equipment and power electronics.
PSPICE, LTSPICE, HSPICE, Mentor Graphics XxDesigner, ORCAD Capture, Mentor Graphics Expedition, Zuken, oscilloscope, current probe, frequency response analyzer, multimeter
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Senior Analog Design Engineer
Phoenix or Chandler or Hillsboro
$191k-$269k/yr HybridFull Time
6+ YOEBSc in EE or related, 6+ years analog/mixed-signal design experience for high-speed SerDes or similar, proficiency with Cadence/HSPICE, post-silicon validation, and strong communication and debugging skills.
Cadence Virtuoso/ADE, HSPICE, Cadence, Synopsys, Verilog-A, MATLAB, Python, Tcl
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Principal Analog Design Engineer
Chandler, Arizona, United States
OnsiteFull Time
10+ YOEMSEE required; 10+ years developing mixed-signal ICs, preferably 5+ years as an architect or technical leader. Requires analog transistor-level design, DC-DC architecture, Cadence tools, and English communication.
Cadence Virtuoso, Cadence Spectre, Cadence AMS
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Senior Technical Staff Engineer – IC Analog Design
Chandler, Arizona, United States
OnsiteFull Time
12+ YOESenior IC analog design engineer with 12+ years, DAC/ADC expertise, CMOS design, lab testing, Cadence tools, scripting.
Cadence Virtuoso, Cadence Spectre, MATLAB, Python, Tcl
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Analog Mixed Signal Modeling Engineer (UL - 02)
Austin or Chandler or Greensboro
HybridFull Time
Master's in EE/Computer Eng required. Experience in mixed-signal product development, analog IC design, SystemVerilog RNM, AMS simulators, verification methodologies, and strong analytical and communication skills.
SystemVerilog Real Number Modeling (SV-RNM), Verilog AMS, AMS simulators, System Verilog Assertions, PSL Assertions, Perforce, GIT, UVM, Simulink, Simscape, Python
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Design Engineer
Scottsdale, Arizona, United States
OnsiteFull Time
onsemi: Designs and manufactures semiconductor solutions for power and sensing.
Master's in Electrical Engineering; semiconductor device design; Cadence tools; 3D EM/analog RF tools; strong communication and leadership.
Cadence, TCAD, 3D EM Simulation, Analog/RF analysis tools, LVS, DRC, Schematic capture
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Senior Electrical Engineer (AZ, Scottsdale)
Scottsdale, Arizona, United States
OnsiteFull Time
Design, analyze, test, and troubleshoot analog, digital, mixed-signal, and embedded electronic systems; support system integration, verification/validation, manufacturing transfer, and sustaining engineering for medical devices.
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I/O Design Engineer
Chandler, Arizona, United States
$110k-$176k/yr OnsiteFull Time
6+ YOERequires an MS or PhD in Electrical Engineering, 6+ years of I/O or analog circuit design experience, and proficiency with Cadence Virtuoso, SPICE/Spectre, CMOS processes, and I/O protocols.
Cadence Virtuoso, SPICE, Spectre, Verilog, Synopsys Liberty, IBIS, GPIO, I2C, I3C, eMMC, RGMII, SPMI
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Mixed-Signal Engineer
Tempe or San Francisco or Phoenix
$130k-$170k/yr HybridFull Time
4+ YOEBS/MS in EE,4+ years mixed-signal hardware design,high-speed PCB and analog fundamentals,lab experience with oscilloscopes and analyzers,and experience interfacing data converters to FPGAs.
Altium, Cadence Allegro, JESD204, SerDes, VHDL, Verilog, SystemVerilog, Xilinx, AMD, Intel, oscilloscope, spectrum analyzer, network analyzer
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Electrical Engineer / Counter-UAS
Gilbert, Arizona, United States
OnsiteFull Time
5+ YOEBachelor's in EE,5+ years electrical design and system integration,experience with power distribution,analog/digital circuitry,PCB tools,EMI/EMC,communication protocols,and ability to obtain security clearance.
Altium, OrCAD, KiCad, UART, SPI, I2C, Ethernet, CAN
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Principal Design Engineer
Chandler or Phoenix or Raleigh or Durham
OnsiteFull Time
10+ YOEBSEE/MSEE with 10+ years experience in precision analog/mixed-signal design; transistor-level design ownership, system-to-block requirements translation, DFT/simulation, EMR of product development; familiarity with Cadence AMS, JAMA, GIT; System Verilog desired.
Cadence Analog and Mixed Signal Tool Suite, JAMA, GIT, system Verilog
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