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Sr Principal ASIC FPGA Engineer
Scottsdale, Arizona, United States
$182k-$202k/yr OnsiteFull Time
8+ YOEBachelor's in Electrical/Computer Engineering or related +10 years (or Master's +8 years); TS/SCI clearance preferred/obtainable; expertise in ASIC/FPGA design, verification, simulation, and technical leadership; Microsoft Office proficiency.
Microsoft Office
1mo
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Advanced ASIC FPGA Engineer- (Sign-on Bonus Available)
Scottsdale, Arizona, United States
$123k-$136k/yr HybridFull Time
5+ YOEBachelor's in ECE or related STEM plus 5+ years experience (or Master's +3). Must be U.S. citizen and able to obtain Top Secret/SCI clearance. Proficient in VHDL/Verilog/SystemVerilog, ASIC/FPGA tool flow, scripting (Tcl/Python/Perl), and technical communication.
VHDL, Verilog, SystemVerilog, SVA, OVM, UVM, QuestaSim, Questa CDC, ISE, Vivado, Libero, Precision, Synplify, Tcl, Python, Perl, Xilinx, Microchip, Oscilloscope, Logic Analyzer, ChipScope, Microsoft Office
2mo
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Advanced ASIC FPGA Verification Engineer for Crypto and Cross Domain Solutions
Scottsdale, Arizona, United States
$135k-$150k/yr OnsiteFull Time
5+ YOEBachelor's in Electrical/Computer Engineering plus 5+ years (or Master's with 3+ years); DoD Secret clearance; U.S. citizenship.
SystemVerilog, VHDL, UVM, QuestaSim, ModelSim, Vivado, Jenkins, GitLab CI, Python, Tcl, Bash, Perl
2mo
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Advanced ASIC FPGA Design Engineer for Crypto and Cross Domain Solutions
Scottsdale, Arizona, United States
$135k-$150k/yr OnsiteFull Time
5+ YOEBachelor's in Electrical/Computer Engineering with 5+ years' experience or Master's with 3+ years; U.S. citizenship and DoD Secret clearance required.
Xilinx Vivado, Microchip Libero, VHDL, Verilog, SystemVerilog, QuestaSim, ModelSim, CI/CD, Python, Tcl
1mo
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ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead (Remote)
San Jose or Research Triangle Park or Acton or Dallas or Tempe or Cary or Carlsbad or Colorado Springs
$184k-$264k/yr RemoteFull Time
3+ YOEBachelor's/MS/PhD in Electrical Engineering with 3+ to 8+ years SI/PI experience; expertise in high-speed design, SI/PI simulation, layout review, SPICE; mentoring and leadership experience.
Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, Ansys EM, SPICE, Vector Network Analysis, IBIS
3w
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Senior Digital Engineer
Chandler, Arizona, United States
OnsiteFull Time
5+ YOE5+ years digital design experience, degree in electrical/computer discipline, fluent Verilog/SystemVerilog, ASIC methodology, lint/CDC/RDC experience, RTL and gate-level debug, English proficiency, willing to travel.
Verilog, SystemVerilog, Lint, CDC, RDC, UPF, UVM, AMBA, I2C, STA
2mo
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Principal Engineer - Digital Design
Chandler, Arizona, United States
OnsiteFull Time
10+ YOEBachelors with 10+ years in digital design; RTL coding/verification; USB/Ethernet PHY knowledge; Verilog/SystemVerilog; UVM/VMM a plus; ASIC flow; CAD tools; timing; scripting.
Verilog, SystemVerilog, UVM, Questa, Design Compiler, Formality, Spyglass, Crossing Clock domain checking, lint, stuck-at, At-Speed scan, Scripting (C, TCL, Perl, Awk, UNIX shell), CVS, Perforce, DesignSync
1mo
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Principal Engineer Electrical
Gilbert, Arizona, United States
$98k-$148k/yr OnsiteFull Time
5+ YOEBachelor's in STEM +5 years (or Master's +3 / PhD +1) experience in RTL/HDL FPGA/ASIC design for aerospace/space, proficiency in FPGA design flow, verification, synthesis, timing and power analysis; strong communication and problem solving.
HDL, RTL, Xilinx ISE/Vivado, Mentor Graphics ModelSim/QuestaSim, Synplify, System Verilog, Universal Verification Methodology (UVM), Signal Generators, Logic Analyzers, Digital Oscilloscopes, Embedded FPGA Debugging tools
1mo
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DFT Engineer (CE-64000920)
Austin or Chandler or Greensboro
HybridFull Time
2+ YOEMSEE with 2+ years or BS with relevant experience; hands-on ASIC DFT design and verification; experience with FastScan, TestKompress, TetraMAX, Test Compiler; MBIST, scan/ATPG, Verilog/SystemVerilog/VHDL; scripting (Perl, Python, TCL); strong communication.
FastScan, TestKompress, TetraMAX, Test Compiler, Verilog, SystemVerilog, VHDL, Perl, Python, TCL
2w
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Staff Digital Design Engineer
Chandler, Arizona, United States
HybridFull Time
11+ YOE>10 years digital design experience, degree in EE/CE/CS or related, fluent Verilog/SystemVerilog, ASIC methodology knowledge, Lint/CDC/RDC experience, RTL and gate-level debug, English proficiency, travel readiness.
Verilog, SystemVerilog, Lint, CDC, RDC, UPF, UVM, AMBA, I2C, STA
3w
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
5d
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Technical Program Management Lead (Member of Technical Staff)
Vancouver or Chandler or California
HybridFull Time
10+ YOEBachelor's in engineering or CS, 10+ years program management in semiconductor/ASIC/hardware, strong silicon development knowledge, vendor management, schedule and risk management, experience with Jira/Confluence/Smartsheet/Microsoft Project.
Jira, Confluence, Smartsheet, Microsoft Project