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Analog Layout Engineer
Beaverton, Oregon, United States
OnsiteFull Time
Experienced in analog/mixed-signal layout for SerDes, PLLs, and sensors; able to translate circuit designs into silicon, collaborate with designers, and optimize custom analog designs.
2mo
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Analog Layout Designer
Irvine, California, United States
$108k-$173k/yr OnsiteFull Time
8+ YOE8+ years experience in analog/RF layout, floorplanning, analog module integration; Cadence tools experience; knowledge of sub-micron processes; strong debugging of DRC/LVS/antenna; FinFET experience preferred.
Cadence, TSMC processes
2mo
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Analog IC Layout Engineer
Fremont, California, United States
$83k-$139k/yr OnsiteFull Time
2+ YOE2+ years analog/mixed-signal IC layout; 1+ year FinFET; problem-solving ability; strong layout skills.
Analog layout, Mixed-signal layout, SKILL, TCL, Shell, C/C++, Python
1mo
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Staff Analog Layout Engineer
San Jose or Hsinchu
OnsiteFull Time
3+ YOESenior/Staff level IC layout engineer with 3-8+ years in deep-submicron analog/RF layouts; strong EDA/tool experience and EM/IR knowledge.
Cadence Virtuoso, Synopsys Custom Compiler, Mentor Calibre, Siemens ICV
1w
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Principal Analog Layout Engineer
San Diego, California, United States
$152k-$225k/yr OnsiteFull Time
8+ YOEDrawing layouts for analog/mixed-signal schematics using Cadence Virtuoso VXL or Synopsys Custom Compiler, resolving PV issues with Calibre, strong communication and problem-solving; advanced degree plus 8+ years experience preferred.
Cadence Virtuoso VXL, Synopsys Custom Compiler, Mentor Graphics Calibre
1mo
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Staff Custom Analog Layout Engineer
San Jose or United States
$139k-$259k/yr HybridFull Time
10+ YOEBS degree or equivalent; 10+ years in analog/mixed-signal layout design; proficient with layout tools and DRC/LVS/ERC flows.
Virtuoso, Laker, Calibre, PVS, IC Validator, DRC/LVS/ERC tools, RC extraction, EM/IR analysis
2mo
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Senior Quantum Analog Layout Engineer
Redmond, Washington, United States
$120k-$235k/yr HybridFull Time
1+ YOEDoctorate+1 yr OR Master+4 yrs OR Bachelor+6 yrs (or equivalent experience); eligible for security/export screening and citizenship verification; experience with analog mask layout, EDA tools, and coordinating vendors/staff.
Cadence Virtuoso, Cadence, Mentor, Synopsys, Electronic Design Automation (EDA), Schematic-Driven Layout (SDL), Graphic Database System (GDS), Process Design Kits (PDK)
3mo
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Analog Layout Engineer (San Francisco, CA, US)
San Francisco, California, United States
$98k-$204k/yr OnsiteFull Time
6+ YOE6+ years in analog/RF layout; experience with floor planning, placement, routing; strong deep sub-micron/FinFET knowledge; BS in EE or related field.
2mo
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Staff Analog IC Layout Engineer
San Diego, California, United States
$120k-$180k/yr OnsiteFull Time
8+ YOEBachelor's in Electrical Engineering; 8+ years analog/mixed-signal IC layout; LVS/DRC verification with Cadence/Mentor; strong CMOS knowledge.
Cadence, Mentor Graphics, Tanner, Calibre
1mo
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Analog/Mixed-Signal Layout Engineer
Woburn, Massachusetts, United States
$141k-$200k/yr OnsiteFull Time
6+ YOE6+ years custom analog/mixed‑signal layout experience; bachelor’s in EE/CE; proficiency with Virtuoso L/XL, Calibre, parasitic extraction (StarRC/QRC); EM/IR analysis; double/multiple patterning; strong communication and teamwork.
Cadence Virtuoso L/XL, Calibre, StarRC, QRC, SOS, ICManage, SKILL
2mo
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Analog/RF IC Layout Design Engineer
Colorado Springs or Santa Clara
$120k-$200k/yr OnsiteFull Time
7+ YOEBS/MS in Electrical Engineering; 7+ years analog IC layout; 5+ years Cadence Virtuoso Layout XL; DRC/LVS/meter densities; BiCMOS 130 nm+; device matching knowledge; multi-design capability; SVN/Cliosoft/SOS experience; strong teamwork.
Cadence Virtuoso, DRC, LVS, Mentor Calibre, OCEAN, Scripting
2mo
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Lead Analog IC Layout Engineer
Wilmington or Limerick
$135k-$202k/yr OnsiteFull Time
7+ YOELead designer for complex IC layout; 7+ years of experience; Cadence Virtuoso; LVS/DRC knowledge; Electrical/Computer Engineering degree.
Cadence Virtuoso, LVS, DRC
1mo
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Principal/Senior High-Speed Analog Layout Engineer
Irvine or San Jose or Ottawa
OnsiteFull Time
10+ YOE10+ years analog/mixed-signal layout experience in advanced CMOS/FinFET (TSMC preferred), expertise with Cadence Virtuoso, Calibre, Pegasus, LVS/DRC/PERC/ERC flows, and leadership/mentoring experience; scripting with SKILL/TCL/Python a plus.
Cadence Virtuoso, Calibre, Pegasus, SKILL, TCL, Python
2mo
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Senior Quantum Analog Layout Engineer (200036791)
United States
OnsiteFull Time
Not specified in posting.
19h
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Layout Designer
Dallas, Texas, United States
OnsiteFull Time
5+ YOEAssociates degree and minimum 5 years layout experience; experience with advanced analog layout, reliability/ESD/electromigration, mentoring, and process/methodology improvements.
CAD
4d
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ASIC Layout Designer
Boulder or Louisville or Beaverton
OnsiteFull Time
7+ YOEMinimum 7 years RF/analog/mixed-signal layout experience; proficient in broadband RF/high-speed layout, PDKs, floor planning, parasitic minimization, physical verification, and mentoring teams.
Cadence Virtuoso Schematic L, Layout L, Layout XL, Cadence Assura, PVS, Pegasus, Calibre, customIC, Solido, Aprisa, Questa, SVN, SOS, Synchronicity, IC Manage, Skill, Python, Ruby, Shell, Cadence Allegro PCB Design
2mo
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IC Layout Manager (Analog/Mixed Signal)
Richardson, Texas, United States
HybridFull Time
10+ YOE10+ years IC layout experience in mixed-signal/full-custom chips, tape-out delivery, expertise with physical verification (DRC/LVS/EM-IR), Cadence/Synopsys tool flows, strong communication, and ITAR U.S. Person eligibility.
Cadence Virtuoso, Synopsys Custom Compiler, Calibre, PVS, IC Validator, LVS, DRC, EM/IR
3d
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RFIC Layout Designer (RFIC Engineering)
Redmond or Irvine or Palo Alto
OnsiteFull Time
1+ YOEIC layout experience for RF/analog designs, 1+ years professional layout or 3+ years without degree; skills in analog/RF layout, advanced-node processes, scripting, revision control, and Linux; ITAR eligibility required.
Skill, shell scripting, Perl, Python, Linux, GDS
1d
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Layout Design Engineer
Austin, Texas, United States
OnsiteFull Time
10+ YOEAssociates degree in electronic/IC layout or related and 10+ years IC layout experience; proficiency in analog/mixed-signal layout, floor planning, LVS debug, and ESD/DFM concerns.
Cadence Virtuoso XL, Mentor's Calibre
2mo
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Mask Layout Designer
San Diego, California, United States
$41-$61/hr OnsiteFull Time
2+ YOEExperience designing custom high-frequency RF/analog chip layouts, proficiency with layout/verification tools and scripting (SKILL, Python, Perl), and ability to mentor or lead layout teams; degree and years of experience options provided.
SKILL, Python, Perl, Cadence Virtuoso XL, Cadence, Siemens Calibre DRC/ERC/LVS, LVS, rmap
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