3d
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Senior ASIC/FPGA Design Engineer
McKinney, Texas, United States
$87k-$165k/yr OnsiteFull Time
5+ YOEBachelor's in STEM,5+ years FPGA/ASIC design and RTL experience,experience with Xilinx/Altera and high-speed interfaces,Python/Perl/Shell scripting,ability to obtain U.S. government security clearance;U.S. citizenship required.
Xilinx, Altera, Python, Perl, Shell, System Verilog, UVM, MATLAB, PCI/PCIe, VPX, Gb Ethernet, Ienterlaken
2mo
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ASIC & FPGA Design Engineer Sr
Grand Prairie, Texas, United States
$101k-$201k/yr HybridFull Time
3+ YOEBachelor's in EE or related (Master's preferred); 3+ years FPGA design and verification experience; proficiency in VHDL/Verilog/SystemVerilog, FPGA toolsets (Vivado/Vitis), simulation (Synopsys VCS), GitLab; U.S. citizenship and ability to obtain DoD Secret clearance.
VHDL, Verilog, SystemVerilog, UVM, SystemC, Python, GitLab, Vivado, Vitis, Vitis HLS, Synopsys VCS, Synopsys EDA tools, C/C++, MATLAB/Simulink, Synopsys Synplify, NCSim, ChipScope, tcpdump, Wireshark, UltraScale
1mo
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ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead (Remote)
San Jose or Research Triangle Park or Acton or Dallas or Tempe or Cary or Carlsbad or Colorado Springs
$184k-$264k/yr RemoteFull Time
3+ YOEBachelor's/MS/PhD in Electrical Engineering with 3+ to 8+ years SI/PI experience; expertise in high-speed design, SI/PI simulation, layout review, SPICE; mentoring and leadership experience.
Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, Ansys EM, SPICE, Vector Network Analysis, IBIS
1w
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Senior Program Manager
Allen, Texas, United States
OnsiteFull Time
onsemi: Designs and manufactures semiconductor solutions for power and sensing.
15+ YOEBachelor's in EE or related, 15+ years semiconductor experience with program/product development, ASIC/mixed-signal PM experience, strong technical, analytical and communication skills, ability to lead cross-functional teams.
RTL, DV, DFT, PD, emulation, FW, ASIC
3mo
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Principal Digital Design Engineer / Chip Lead
Minneapolis or Boise or Folsom or Richardson or San Jose
$206k-$410k/yr OnsiteFull Time
10+ YOE10+ years in digital/ASIC design with chip/design lead ownership; SystemVerilog RTL; synthesis/timing tools; cross-team integration leadership.
SystemVerilog, DC, Genus, PrimeTime, Tempus
2mo
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Staff HBM Design Architect - DFT
Richardson or Folsom
$146k-$297k/yr OnsiteFull Time
5+ YOEDefine end-to-end DFT architectures; develop test flows; wafer probe/final test experience; 5+ years in DRAM/ASIC DFT.
Scan, MBIST, JTAG, Boundary Scan, Wafer Probe, Final Test
1w
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Senior Principal Firmware Engineering Lead
McKinney, Texas, United States
$132k-$252k/yr OnsiteFull Time
10+ YOEActive transferable DoD Secret clearance, U.S. citizenship, STEM degree, ~10+ years FPGA/ASIC firmware experience with VHDL/Verilog, leadership, and system-level FPGA design and verification skills.
Xilinx, Altera, Microsemi, VHDL, Verilog, System Verilog, UVM, Veloce, ARM, Microblaze, Nios, High Level Synthesis (HLS)
2w
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FPGA ENGINEER II
McKinney, Texas, United States
$69k-$131k/yr OnsiteFull Time
2+ YOEU.S. citizen with active DoD Secret clearance, STEM degree and ≥2 years FPGA/ASIC experience (VHDL/Verilog/SystemVerilog), experience with AMD/Altera/Microchip toolchains, lab integration and verification skills.
VHDL, Verilog, SystemVerilog, AMD Vivado, Altera Quartus Prime Pro, Libero, High Level Synthesis (HLS)
1mo
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Design Engineer, HBM DFT
Richardson, Texas, United States
OnsiteFull Time
0+ YOEBachelor's or Master’s in EE/CE, 0–3 years experience or internship in ASIC/SoC/DFT, familiarity with digital design and synthesizable RTL (SystemVerilog/Verilog), and ability to support DFT implementation, validation, and debug.
SystemVerilog, Verilog, IJTAG, P1500, ATPG, MBIST
1w
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System Architect, Custom Silicon
Richardson, Texas, United States
$171k-$296k/yr OnsiteFull Time
Proven track record delivering complex semiconductor products; expertise in system architecture for ASICs/SoCs/MCUs; processor, memory, interconnect and security knowledge; cross-functional leadership and customer-facing skills; bachelor\u0002s degree required.
1mo
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DFT Engineer (Design for Testability) - Staff
Richardson, Texas, United States
OnsiteFull Time
5+ YOEBachelor's/Master's in EE/CE or equivalent, strong digital design and DFT fundamentals (scan, MBIST, JTAG), RTL experience (SystemVerilog/VHDL), familiarity with semiconductor test flows, and 5+ years DRAM or ASIC DFT design/verification experience.
SystemVerilog, VHDL, RTL, JTAG, MBIST
4d
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Aircraft Structural Dynamics Engineer
Wichita or Tucson or Opa-locka or Fort Worth or Windsor
OnsiteFull Time
15+ YOEUniversity engineering degree, 15+ years technical experience (10+ in aeronautics), 5+ years FPGA/ASIC or embedded software, knowledge of airborne software/hardware standards, DOORS/JAMA experience, C/C++/Ada95/Assembly/Python, OIQ membership preferred.
DOORS, JAMA, C, C++, Ada95, Assembly, Python
3mo
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Principal Engineer Digital Design
Irvine or California or Dallas or Texas
$164k-$241k/yr HybridFull Time
12+ YOEBachelor's degree in EE/Computer Engineering, 12+ years RTL design experience (Verilog/System Verilog), DSP algorithm implementation, fixed-point math, MATLAB/C/C++, FPGA/ASIC experience, and familiarity with EDA tools (Synopsys Design Compiler, Cadence).
Verilog, System Verilog, HDL, MATLAB, Simulink, C, C++, Synopsys Design Compiler, Cadence