4d
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ASIC Engineer, Architecture
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOE6+ years in ASIC/silicon engineering with experience in performance modeling; proficiency in C++ and Python; BS in CS/CE or equivalent; experience with SystemC, assembly, and ASIC performance analysis.
C++, Python, SystemC, CUDA, SystemVerilog, VHDL
1mo
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Distinguished Engineer, ASIC (CONTRACT)
Burlington or New York or San Francisco
HybridContract, Temporary
8+ YOE8–12+ years in digital IC/ASIC/SoC design; strong RTL SystemVerilog; tapeout experience; cross-functional collaboration.
SystemVerilog, Verilog, RTL, ASIC, SoC, clock_domain, PPA tools
2w
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ASIC Scientist
United States
$144k-$198k/yr OnsiteFull Time
Ph.D. or Master’s in EE/Physics/Computer Engineering/Microelectronics; experience in ASIC/mixed-signal IC design, semiconductor device physics, and use of IC design and simulation tools; strong analytical and collaboration skills.
Cadence Virtuoso, Spectre, HSPICE
3mo
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ASIC Architect
Santa Clara, California, United States
$192k-$287k/yr OnsiteFull Time
15+ YOE15+ years in Electrical/Computer Engineering with Masters or 10+ years with PhD; strong architecture leadership; experience with ASIC product architectures; knowledge of PCIe, CXL, UALink, Ethernet; ARM CPU subsystem; hardware/SoC co-design and security.
PCIe, CXL, Ethernet, UALink, Data Network Switching, ARM CPU Subsystem
2mo
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ASIC Engineer 2
Longmont, Colorado, United States
$143k-$176k/yr OnsiteFull Time
Define ASIC design/verification requirements; HDL/RTL, scripting; physical design basics; review requirements and collaborate with architects.
Perl, Python, C, Unix shell, Verilog, SystemVerilog, VHDL, RTL
3d
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Senior ASIC Engineer
Santa Clara, California, United States
$127k-$190k/yr OnsiteFull Time
2+ YOE2+ years ASIC verification experience, UVM experience, ability to build UVM testbenches, knowledge of digital logic, SoC architecture, AMBA protocols, scripting, and verification strategy.
UVM, ARM, AMBA, AHB, AXI
3mo
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ASIC Design Engineer
California or United States
OnsiteFull Time
10+ YOEBachelor's degree with 10+ years of experience in ASIC design and hardware architecture.
2w
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Principal ASIC Engineer
El Segundo, California, United States
$211k-$285k/yr OnsiteFull Time
20+ YOEUS-person requirement for security clearance, BS in engineering or related field, ~20+ years ASIC/FPGA design & verification experience, SystemVerilog/UVM expertise, hardware integration and team leadership.
SystemVerilog, System Verilog Assertions, Palladium, UVM, Make, Perl, Python, svn, cvs, git, Linux, JESD204C, PCIe, Ethernet
2w
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Principal ASIC Engineer
El Segundo, California, United States
$211k-$285k/yr OnsiteFull Time
20+ YOEU.S. person required for U.S. security clearance; BS in engineering or related; ~20 years ASIC/FPGA design and verification experience; SystemVerilog expertise; hardware integration and team leadership experience.
SystemVerilog, System Verilog Assertions, UVM, HDL, Palladium, Make, Perl, Python, svn, cvs, git, Linux, JESD204C, PCIe, Ethernet
3mo
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ASIC Design Engineer
Sunnyvale, California, United States
$120k-$243k/yr OnsiteFull Time
3+ YOEDesign engineer with strong Verilog/SystemVerilog, ASIC design, RTL timing and verification experience.
Verilog, SystemVerilog, RTL, EDA tools, Python, Perl
3mo
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Sr. ASIC Design Engineer (Starshield)
Hawthorne, California, United States
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical or computer engineering or computer science; 5+ years RTL/FPGA/ASIC experience.
Verilog, SystemVerilog, RTL, FPGA, ASIC, Python, TCL, EDA tools (HDL simulators: VCS, Questa, IES), Spyglass, Xilinx Vivado, Quartus II, AXI, AHB
2mo
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Sr. Engineer, ASIC Design
San Jose, California, United States
$160k-$192k/yr OnsiteFull Time
1+ YOEBS or MS in Electrical/Computer Engineering; 1+ years ASIC design; Verilog; ASIC verification tools; scripting; ability to work independently.
Verilog, Xcelium, VCS, Questa, Python, C, C++
3mo
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ASIC Design Engineer
Sunnyvale, California, United States
$120k-$243k/yr OnsiteFull Time
3+ YOEDesign ASICs using Verilog/SystemVerilog; strong digital design, timing, RTL, verification, and collaboration with cross-functional teams.
Verilog, SystemVerilog, EDA tools, Synthesis, Lint, Perl, Python
2mo
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ASIC Design Engineer
United States
RemoteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
0+ YOEBS or MS in Electrical Engineering or Computer Engineering; 0–2 years ASIC digital design; SystemVerilog/Verilog RTL; digital design fundamentals; cross-functional collaboration.
SystemVerilog, Verilog, RTL, Synthesis, Timing
3mo
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ASIC Design Engineer
Irvine or Andover
$127k-$203k/yr OnsiteFull Time
7+ YOEBachelors with 12+ years, or Masters with 10+ years, or PhD with 7+ years in ASIC design/implementation; expertise in synthesis, floorplanning, place-and-route, timing, power, SI, and DFT.
Synthesis, Place and Route, Clock Methodology, Power Planning, Timing Analysis, Signal Integrity, DFT, EDA Tools
3w
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ASIC Engineer, Annapurna Labs
Austin, Texas, United States
OnsiteFull Time
Bachelor's in Electrical Engineering (required); design and verification experience for ASICs/SoCs; strong SystemVerilog skills; experience debugging architectures and verifying IP-to-system levels; familiarity with microarchitecture, synthesis, timing, and RTL development.
SystemVerilog, Python, Perl, ARM
3mo
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Principal ASIC Architect
Sunnyvale, California, United States
HybridFull Time
15+ YOELead ASIC architecture and design for high-performance AI processors; 15+ years silicon design; Verilog RTL; C/C++; SystemC; MS/PhD in EE/related field.
Verilog, SystemVerilog, RTL_verification, C++, Python, SystemC
1w
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Project Lead ASIC Engineer
Cambridge, Massachusetts, United States
$95k-$245k/yr HybridFull Time
5+ YOEBachelor's in engineering required (masters preferred); 5+ years ASIC hardware engineering experience with bachelor's (less with advanced degrees); ability to design/simulate transistor-level circuits, lead small teams, and work with fabrication/test sites.
3mo
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ASIC Verification Engineer
Austin, Texas, United States
$116k-$190k/yr HybridFull Time
2+ YOEBS/MS in Electrical or Computer Engineering; 2+ years ASIC/RTL verification; pre-silicon verification (UVM, SystemVerilog); RTL verification; Perl/Python; debugging; exposure to verification tools; strong communication.
UVM, SystemVerilog, Perl, Python, dc_shell, VCS, GDB, Debussy
3w
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ASIC Technology Librarian
Sunnyvale, California, United States
$138k-$198k/yr OnsiteFull Time
4+ YOEBachelor's in EE/CE/CS or equivalent experience, 4 years managing vendor engagements and library delivery schedules in an ASIC design environment, LEC and library validation tool experience, familiarity with foundry PDKs, and scripting in Tcl or Python.
Formality, Conformal, Siemens Solido Crosscheck, Fractal Crossfire, TSMC, Synopsys, PDKs, Tcl, Python
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