16 asic design verification engineer jobs at 8 companies in Boston, MA
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ASIC Design Verification Engineer
Irvine or Andover or Broomfield
$129k-$207k/yr OnsiteFull Time
3+ YOEConstrained-random design verification experience using System Verilog/UVM, coverage-driven methodologies, experience with VCS/Incisive and scripting (Python/Perl). Degree with significant related experience required (varies by degree).
System Verilog, UVM, VCS, Incisive, Python, Perl
3d
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Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU
Santa Clara or Austin or Westford or Durham or California
$136k-$265k/yr HybridFull Time
5+ YOEBachelor's or master's degree in engineering or computer science, 5+ years' experience, ASIC workflows, UVM, Verilog/SystemVerilog, simulation tools, and Python, Perl, or systems programming.
Python, Perl, Verilog, SystemVerilog, UVM, VCS, Verdi, Xcelium
3d
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Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU
Santa Clara or Westford or Austin or Durham or California
$136k-$265k/yr OnsiteFull Time
5+ YOEBS/MS or equivalent experience; 5+ years relevant experience; ASIC workflows, UVM, Verilog/SystemVerilog, simulation/debug tools, Python or Perl, and root-cause analysis skills required.
UVM, Verilog, SystemVerilog, VCS, Verdi, Xcelium, Python, Perl
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Staff Design Verification Engineer – Coherent Interconnect
Boston or Austin
OnsiteFull Time
7+ YOELead verification for cache-coherent interconnect; 7+ years ASIC/SoC verification; SystemVerilog/UVM expertise; strong debugging and collaboration skills.
SystemVerilog, UVM, Verilog, Python
4d
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Principal Design Verification Engineer – CPU Coherent Interconnect
Santa Clara or Austin or Boston
$231k-$283k/yr OnsiteFull Time
12+ YOEBS, MS, or PhD in a relevant field and 12+ years of CPU, subsystem, SoC, or ASIC functional verification experience. Requires SystemVerilog, cache coherence, subsystem verification, and Python or similar scripting skills.
SystemVerilog, Python
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Senior Staff Design Verification Engineer – Coherent Interconnect
Boston or Austin
OnsiteFull Time
8+ YOE8+ years ASIC/SoC design verification experience, strong SystemVerilog and Python skills, deep knowledge of cache-coherent interconnects and protocols (CHI, ACE, CXL, AXI), BS/MS in EE/CE/CS, strong communication and leadership.
SystemVerilog, Python
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Staff Design Verification Engineer – Coherent Interconnect
Boston or Austin
OnsiteFull Time
7+ YOEBS/ MS in Electrical/Computer Engineering; 7+ years ASIC/SoC verification; strong CXL/CHI/AXI; SystemVerilog/UVM; cache-coherent systems; test plans, coverage; Python scripting.
SystemVerilog, UVM, Python
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Senior Staff Design Verification Engineer – Coherent Interconnect
Boston or Austin
OnsiteFull Time
8+ YOE8+ years ASIC/SoC design verification experience; strong SystemVerilog and Python skills; deep understanding of cache-coherent interconnects, protocols (CHI/ACE/CXL/AXI), test plans, assertions, and coverage models; BS/MS in EE/CE/CS required.
SystemVerilog, Python
2w
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Senior Engineer, Physical Design Engineering (ASIC)
Somerset County or Wilmington
$117k-$161k/yr OnsiteFull Time
5+ YOEExpertise in ASIC/SoC physical design, floorplanning, P&R, timing closure, physical verification, scripting (TCL/Python), and cross-functional collaboration; 5+ years experience preferred.
Cadence, TCL, Python
2mo
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
Nashua or Manchester or Largo or New Hampshire or Florida or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree (or equivalent) with 8+ years experience; ability to obtain Secret clearance; expertise in SystemVerilog/UVM, OVM, VHDL, FPGA/ASIC verification and tools; experience with Mentor Questa or Cadence; strong communication and leadership.
SystemVerilog/UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, MATLAB, Simulink
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
San Diego or Nashua or Austin or Totowa or California or New Hampshire or Texas or New Jersey or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree with 8+ years (or equivalent experience); eligible for Secret clearance; experience with SystemVerilog/UVM/OVM and/or VHDL, Mentor Questa or Cadence tools; FPGA/ASIC verification, test plan development, and strong communication.
SystemVerilog, UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, Matlab, Simulink
1w
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ASIC/FPGA Methodology Engineer (TERADYNE, North Reading, MA)
North Reading, Massachusetts, United States
$155k-$248k/yr OnsiteFull Time
3+ YOEBachelor's or master's degree in electrical or computer engineering, 3+ years of FPGA and embedded design experience, and proficiency with design, verification, CI/CD, and Linux tools.
Verilog, Vivado, Quartus, Jenkins, Docker, Git, Linux, LSF, ClearCase, Artifactory, SystemVerilog, UVM
1d
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MTS Silicon Design Engineer
Boxborough, Massachusetts, United States
OnsiteFull Time
3+ YOEMaster's degree and 3 years of related engineering experience, or bachelor's degree and 5 years. Requires hardware verification, Verilog/SystemVerilog/VHDL, UVM/AVM, C/C++/Python, CPU/GPU/SoC architecture, and pre-silicon verification.
Verilog, SystemVerilog, VHDL, UVM, AVM, C, C++, Python, CPU, GPU, SoC, ASIC, RTL
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Engineer: Sr. Electrical Design Engineer
Cambridge, Massachusetts, United States
$80k-$110k/yr OnsiteFull Time
5+ YOEMaster's in EE, 5+ years product development experience, PCB and embedded hardware design, Altium/Eagle, C/Assembly, verification/validation, FDA/ISO 13485 experience, LabVIEW/MATLAB/Simulink familiarity.
Altium, Autodesk Eagle, C, Assembly, Verilog, VHDL, FPGA, ASIC, LabVIEW, MATLAB, Simulink, Java, Android, oscilloscopes, logic analyzers
1w
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Senior Architect, NVLink
Westford, Massachusetts, United States
$184k-$357k/yr OnsiteFull Time
8+ YOEMS/PhD or equivalent, 8+ years in architecture/design/verification, ASIC design experience, shipped projects in processor and I/O architecture, programming in C++ and Verilog, strong communication and initiative.
C++, Verilog
1w
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Senior Architect, NVLink
Westford, Massachusetts, United States
$184k-$357k/yr OnsiteFull Time
8+ YOEMS/PhD in EE/CS/CE or equivalent experience,8+ years in architecture/design/verification,ASIC and processor/I/O architecture experience,programming in C++ and Verilog,history of shipped projects.
C++, Verilog
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