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ASIC Design Verification Engineer
United States
$200k-$350k/yr RemoteFull Time
8+ YOE8+ years ASIC verification; degree in EE/CE; SystemVerilog UVM; testbenches and coverage-driven verification; experience with EDA tools; scripting (Python/Perl/TCL).
SystemVerilog, UVM, Simulation tools, Cadence tools, Synopsys tools, Mentor Graphics tools, Python, Perl, TCL
3mo
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ASIC design/verification engineer
Durham, North Carolina, United States
$135k-$311k/yr HybridFull Time
6+ YOEDesign and verify VLSI/ASIC; 6-10 years of experience; Bachelors/Masters in Electrical or Computer Engineering; strong VLSI, EDA, HDL, and programming skills.
HDL, EDA tools, VLSI tools, FPGA tools, Scripting languages
2d
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SR ASIC Design Verification Engineer
San Jose, California, United States
$165k-$241k/yr OnsiteFull Time
1+ YOEDegree in electrical/computer engineering or related plus multi-year ASIC verification experience; proficiency in System Verilog and UVM; ASIC verification, simulation, emulation, post-silicon debug experience; Linux and programming (C/C++, Python/Perl).
System Verilog, UVM, Veloce, Palladium, Zebu, HAPS, Linux, C/C++, Python/Perl
3mo
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ASIC Design Verification Engineer
Santa Clara, California, United States
$106k-$172k/yr OnsiteFull Time
3+ YOEBS in EE, CE, or CS; minimum 3 years ASIC verification; SystemVerilog/UVM; test plans, coverage, and debug; Python automation; strong collaboration.
SystemVerilog, UVM, Python, C++, Perl, UNIX Shell
2mo
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Principal Engineer, ASIC Design Verification
San Jose, California, United States
$190k-$240k/yr OnsiteFull Time
12+ YOEMS in Electrical or Computer Engineering; 12+ years ASIC/SoC verification experience; SystemVerilog and UVM expert; verification environment design; scripting for automation.
SystemVerilog, UVM, Scripting (Python, Perl, Tcl, Shell)
3mo
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ASIC design/verification engineer
Durham, North Carolina, United States
$135k-$311k/yr HybridFull Time
6+ YOEBachelor’s or Master’s degree in Electrical or Computer Engineering; 6-10 years in VLSI design/verification; strong HDL/EDA skills.
Hardware description language, Electronic design automation, FPGA tools, Programming and scripting
1mo
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ASIC Design Verification Engineer
Austin, Texas, United States
HybridFull Time
Several years of RTL verification experience in IP/ASIC/SoC, deep SystemVerilog and UVM knowledge, testbench architecture, scripting (TCL/Python/Perl), Linux/GIT experience, and BS/MS in EE/CE or equivalent experience.
SystemVerilog, UVM, TLM, TCL, Python, Perl, Linux, GIT, LSF
3mo
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ASIC design/verification engineer
Durham or United States
$135k-$311k/yr HybridFull Time
6+ YOEBachelor’s or Master’s in Electrical/Computer Engineering; 6-10 years in VLSI design/verification; strong knowledge of VLSI, digital logic, and computer architecture; experience with HDL/EDA tools; proficient in English (written and spoken).
Verilog, SystemVerilog, VHDL, EDA, FPGA tools
1mo
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ASIC Design Verification Engineer
Irvine or Andover or Broomfield
$129k-$207k/yr OnsiteFull Time
3+ YOEConstrained-random design verification experience using System Verilog/UVM, coverage-driven methodologies, experience with VCS/Incisive and scripting (Python/Perl). Degree with significant related experience required (varies by degree).
System Verilog, UVM, VCS, Incisive, Python, Perl
3w
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ASIC Engineer, Design Verification
Sunnyvale or Austin
$178k-$250k/yr OnsiteFull Time
8+ YOEBachelor's in CS/CE or equivalent, 8+ years SystemVerilog/UVM or C/C++ verification, IP/SoC verification experience, EDA and scripting (Python, TCL, Perl, Shell), experience with assertions, formal or emulation.
SystemVerilog, UVM, OVM, C, C++, Python, TCL, Perl, Shell
1mo
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ASIC Design Verification Engineer
Austin, Texas, United States
$156k-$268k/yr OnsiteFull Time
Develop and execute IP verification architectures and test plans using System Verilog, UVM, SystemC, Verilog and C/C++; debug regressions, analyze coverage, and participate in code reviews. BS/MS in engineering or CS required. This role is not eligible for visa sponsorship.
System Verilog, UVM, SystemC, Verilog, C, C++, Linux, Windows, VIP
3w
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Senior ASIC Design Verification Engineer
Seattle, Washington, United States
$170k-$250k/yr OnsiteFull Time
5+ YOEB.S./M.S. in EE/CE or related, 5+ years ASIC/SoC verification experience, strong SystemVerilog/UVM skills, simulation and waveform debug tool experience, scripting (Python/Perl/TCL), and familiarity with industry interfaces and CI/CD.
SystemVerilog, UVM, SystemVerilog Assertions (SVA), VCS, Xcelium, Questa, Verdi, SimVision, Python, Perl, TCL, Git, APB, AHB, AXI, C, C++, CI/CD
5d
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ASIC Design Verification Engineer
Minneapolis, Minnesota, United States
OnsiteFull Time
2+ YOE2+ years IP/SoC verification experience with UVM, SystemVerilog, and Python; bachelor’s or master’s in EE/CE; strong debugging, analytical, and communication skills.
UVM, SystemVerilog, Python
1mo
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Senior ASIC Design Verification Engineer - Terawave
Los Angeles or Seattle or California or Washington or Texas or United States
$230k-$323k/yr RemoteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
8+ YOEBS/MS in EE/CE, 8+ years ASIC/SoC verification experience, deep System Verilog and UVM expertise, verification planning, coverage closure, RTL/debugging, cross-functional collaboration.
System Verilog, UVM, RTL
5d
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ASIC Design Verification Engineer
Minneapolis, Minnesota, United States
OnsiteFull Time
2+ YOEBachelor's or Master's in EE/CE,2+ years IP/SoC verification experience, UVM constrained-random experience, strong SystemVerilog and Python skills, analytical debugging and communication skills.
UVM, SystemVerilog, Python
1mo
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ASIC Design Verification Engineer, TPU Cloud Compute
Sunnyvale, California, United States
$138k-$198k/yr OnsiteFull Time
4+ YOEBachelor's in EE/CE/CS or equivalent, 4+ years design verification experience, proficiency with SystemVerilog/Verilog and UVM, experience across verification lifecycle and SoC projects, familiarity with ASIC interfaces and memory architecture.
SystemVerilog, Verilog, Universal Verification Methodology (UVM)
1mo
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Senior ASIC Verification Engineer
Austin, Texas, United States
$136k-$265k/yr HybridFull Time
5+ YOEBS/MS in Electrical or Computer Engineering (or equivalent), 5+ years design verification experience, UVM/SystemVerilog, ASIC flow, Perl or Python, familiarity with synthesis/simulation and debug tools.
SystemVerilog, UVM, Perl, Python, dc_shell, VCS, Debussy, GDB
1w
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Sr. ASIC Design Verification Engineer (Silicon Engineering)
Irvine, California, United States
$165k-$260k/yr OnsiteFull Time
5+ YOEBachelor's in electrical or computer engineering,5+ years design verification experience, proficiency with verification methodologies and scripting, strong problem-solving and OOP skills.
UVM, OVM, VMM, Python, RTL
1mo
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ASIC Design Verification Engineer
Mountain View, California, United States
$175k-$215k/yr HybridFull Time
3+ YOE3+ years experience with UVM/SystemVerilog, constrained-random, functional coverage, SVA; strong RTL debug skills; Python proficiency; excellent communication and analytical abilities.
UVM, SystemVerilog, SVA, Python, C, C++, UPF, PCIe Gen 5, PCIe Gen 6, DDR5, Ethernet, LLMs
3mo
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Sr. Staff ASIC Verification Engineer
Palo Alto, California, United States
$237k-$296k/yr OnsiteFull Time
10+ YOETypically 10+ years in ASIC design verification; BS/MS or PhD in Electrical or Computer Engineering; deep computer architecture; NoC; UPF/CPF; Systolic Arrays/NPUs; CNN/Transformer mapping; compilers/toolchains.
SystemVerilog, UVM, SVA, ISO 26262, FIA, Emulation, FPGA
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