Apache Junction • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Apache Junction • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Apache Junction • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Apache Junction • 50 milesRemote · Hybrid · Onsite · Field · All Environments
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Sr Principal ASIC FPGA Engineer
Scottsdale, Arizona, United States
$182k-$202k/yr OnsiteFull Time
8+ YOEBachelor's in Electrical/Computer Engineering or related +10 years (or Master's +8 years); TS/SCI clearance preferred/obtainable; expertise in ASIC/FPGA design, verification, simulation, and technical leadership; Microsoft Office proficiency.
Microsoft Office
3mo
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Principal FPGA/ASIC Engineer - Level 3
Gilbert, Arizona, United States
$79k-$119k/yr HybridFull Time
1+ YOEBachelor's in STEM with 5+ yrs FPGA design experience (or MS with 3+ yrs, PhD with 1+ yr); HDL/HDL verification, FPGA design flow, aerospace experience, and ability to obtain DoD Top Secret clearance.
HDL, RTL, System Verilog, Universal Verification Methodology (UVM), Xilinx ISE, Vivado, Mentor Graphics ModelSim, QuestaSim, Synplify, Electronic Design Automation (EDA) Tools, Signal Generators, Logic Analyzers, Digital Oscilloscopes, Embedded FPGA Debugging tools
3mo
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Principal FPGA/ASIC Engineer - Level 3
Gilbert, Arizona, United States
$79k-$119k/yr OnsiteFull Time
5+ YOEBachelor’s/Master’s/PhD in STEM with FPGA/HDL design experience; space/A&D applications; DoD Top Secret clearance achievable; 5+ yrs (Bachelors), 3+ yrs (Masters), 1+ yr (PhD).
Xilinx Vivado, ModelSim/QuestaSim, Mentor Graphics, Synplify, SystemVerilog, UVM, RTL, HDL design
3w
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ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead (Remote)
San Jose or Research Triangle Park or Acton or Dallas or Tempe or Cary or Carlsbad or Colorado Springs
$184k-$264k/yr RemoteFull Time
3+ YOEBachelor's/MS/PhD in Electrical Engineering with 3+ to 8+ years SI/PI experience; expertise in high-speed design, SI/PI simulation, layout review, SPICE; mentoring and leadership experience.
Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, Ansys EM, SPICE, Vector Network Analysis, IBIS
3d
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Staff Digital Systems Engineer
Phoenix, Arizona, United States
$185k-$202k/yr OnsiteFull Time
10+ YOEBachelor's in EE/CE, 10+ years designing FPGA/ASIC/SoC-based digital hardware, board bring-up and lab debug, high-speed interface and timing analysis, signal integrity collaboration, strong communication and leadership.
FPGA, ASIC, DDR, PCIe, Ethernet, SerDes, LVDS, SPI, I2C, Linux
3mo
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Design Verification Engineer
Austin or Chandler or Greensboro
HybridFull Time
0+ YOEBachelor/Master/PhD in Electrical/Computer Engineering or related field; 2+ years with Bachelors; strong HDL/SystemVerilog/UVM; ASIC/silicon verification experience.
Verilog, VHDL, SystemVerilog, UVM
2w
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Lead Certification AEH Engineer
Minneapolis or Phoenix or Clearwater
$140k-$175k/yr HybridFull Time
5+ YOEBachelor's in Engineering/Aerospace, 5+ years ASIC/FPGA HDL design/verification or AEH certification liaison experience, US person required, familiarity with FAA regulations and certification processes preferred.
1w
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Senior Digital Engineer
Chandler, Arizona, United States
OnsiteFull Time
5+ YOE5+ years digital design experience, degree in electrical/computer discipline, fluent Verilog/SystemVerilog, ASIC methodology, lint/CDC/RDC experience, RTL and gate-level debug, English proficiency, willing to travel.
Verilog, SystemVerilog, Lint, CDC, RDC, UPF, UVM, AMBA, I2C, STA
2mo
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Principal Engineer - Digital Design
Chandler, Arizona, United States
OnsiteFull Time
10+ YOEBachelors with 10+ years in digital design; RTL coding/verification; USB/Ethernet PHY knowledge; Verilog/SystemVerilog; UVM/VMM a plus; ASIC flow; CAD tools; timing; scripting.
Verilog, SystemVerilog, UVM, Questa, Design Compiler, Formality, Spyglass, Crossing Clock domain checking, lint, stuck-at, At-Speed scan, Scripting (C, TCL, Perl, Awk, UNIX shell), CVS, Perforce, DesignSync
2mo
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Senior Applications and Solutions Engineer - Foundry Services
Phoenix or Santa Clara or Hillsboro
$122k-$232k/yr HybridFull Time
4+ YOEUS citizen; ability to obtain US government security clearance; 4+ years CMOS/low-power/multi-voltage domain; ASIC design and verification experience; scripting in Python/Perl/Tcl.
Cadence, Synopsys, UPF/CPF, VCLP, Conformal LP, Python, Perl, Tcl
1w
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
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