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ASIC Engineer, Architecture
Sunnyvale or Austin
$178k-$250k/yr OnsiteFull Time
8+ YOEBachelor's (or equivalent), 8+ years in ASIC/silicon engineering, 5+ years in performance modeling; proficiency in C++, Python, SystemC; experience with microarchitectural analysis for data center/AI workloads.
C++, Python, SystemC, SystemVerilog, VHDL
1w
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Principal ASIC Engineer
El Segundo, California, United States
$211k-$285k/yr OnsiteFull Time
20+ YOEUS-person requirement for security clearance, BS in engineering or related field, ~20+ years ASIC/FPGA design & verification experience, SystemVerilog/UVM expertise, hardware integration and team leadership.
SystemVerilog, System Verilog Assertions, Palladium, UVM, Make, Perl, Python, svn, cvs, git, Linux, JESD204C, PCIe, Ethernet
1w
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Principal ASIC Engineer
El Segundo, California, United States
$211k-$285k/yr OnsiteFull Time
20+ YOEU.S. person required for U.S. security clearance; BS in engineering or related; ~20 years ASIC/FPGA design and verification experience; SystemVerilog expertise; hardware integration and team leadership experience.
SystemVerilog, System Verilog Assertions, UVM, HDL, Palladium, Make, Perl, Python, svn, cvs, git, Linux, JESD204C, PCIe, Ethernet
3mo
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ASIC Design Engineer
Sunnyvale, California, United States
$120k-$243k/yr OnsiteFull Time
3+ YOEDesign engineer with strong Verilog/SystemVerilog, ASIC design, RTL timing and verification experience.
Verilog, SystemVerilog, RTL, EDA tools, Python, Perl
1w
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Principal ASIC Engineer
El Segundo, California, United States
$211k-$285k/yr OnsiteFull Time
20+ YOERequires US person eligibility and ability to obtain U.S. Secret clearance, BS in engineering or related field, ~20 years ASIC/FPGA design or verification experience, SystemVerilog expertise, hardware integration/test, and team leadership.
SystemVerilog, System Verilog Assertions, Palladium, Make, Perl, Python, svn, cvs, git, Linux, ARM, JESD204C, PCIe, Ethernet
2mo
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ASIC Engineer 2
Longmont, Colorado, United States
$143k-$176k/yr OnsiteFull Time
Define ASIC design/verification requirements; HDL/RTL, scripting; physical design basics; review requirements and collaborate with architects.
Perl, Python, C, Unix shell, Verilog, SystemVerilog, VHDL, RTL
1mo
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Distinguished Engineer, ASIC (CONTRACT)
Burlington or New York or San Francisco
HybridContract, Temporary
8+ YOE8–12+ years in digital IC/ASIC/SoC design; strong RTL SystemVerilog; tapeout experience; cross-functional collaboration.
SystemVerilog, Verilog, RTL, ASIC, SoC, clock_domain, PPA tools
1mo
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Sr. Engineer, ASIC Design
San Jose, California, United States
$160k-$192k/yr OnsiteFull Time
1+ YOEBS or MS in Electrical/Computer Engineering; 1+ years ASIC design; Verilog; ASIC verification tools; scripting; ability to work independently.
Verilog, Xcelium, VCS, Questa, Python, C, C++
1mo
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ASIC Design Engineer
United States
RemoteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
0+ YOEBS or MS in Electrical Engineering or Computer Engineering; 0–2 years ASIC digital design; SystemVerilog/Verilog RTL; digital design fundamentals; cross-functional collaboration.
SystemVerilog, Verilog, RTL, Synthesis, Timing
3mo
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Sr. ASIC Design Engineer (Starshield)
Hawthorne, California, United States
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical or computer engineering or computer science; 5+ years RTL/FPGA/ASIC experience.
Verilog, SystemVerilog, RTL, FPGA, ASIC, Python, TCL, EDA tools (HDL simulators: VCS, Questa, IES), Spyglass, Xilinx Vivado, Quartus II, AXI, AHB
3d
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Project Lead ASIC Engineer
Cambridge, Massachusetts, United States
$95k-$245k/yr HybridFull Time
5+ YOEBachelor's in engineering required (masters preferred); 5+ years ASIC hardware engineering experience with bachelor's (less with advanced degrees); ability to design/simulate transistor-level circuits, lead small teams, and work with fabrication/test sites.
2w
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ASIC Engineer, Annapurna Labs
Austin, Texas, United States
OnsiteFull Time
Bachelor's in Electrical Engineering (required); design and verification experience for ASICs/SoCs; strong SystemVerilog skills; experience debugging architectures and verifying IP-to-system levels; familiarity with microarchitecture, synthesis, timing, and RTL development.
SystemVerilog, Python, Perl, ARM
2w
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ASIC Design Engineer
Santa Clara, California, United States
$127k-$190k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC design and micro-architecture experience; expertise in RTL design, clocking, CDC/lint analysis, AMBA protocols; proficiency in Python and Perl; experience across full ASIC lifecycle.
Python, Perl, ARM CoreSight, AMBA, AHB, APB, AXI, PCIe, USB, FPGA, SoC
3mo
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ASIC Design Engineer
California or United States
OnsiteFull Time
10+ YOEBachelor's degree with 10+ years of experience in ASIC design and hardware architecture.
3mo
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ASIC Verification Engineer
Austin, Texas, United States
$116k-$190k/yr HybridFull Time
2+ YOEBS/MS in Electrical or Computer Engineering; 2+ years ASIC/RTL verification; pre-silicon verification (UVM, SystemVerilog); RTL verification; Perl/Python; debugging; exposure to verification tools; strong communication.
UVM, SystemVerilog, Perl, Python, dc_shell, VCS, GDB, Debussy
3mo
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ASIC Design Engineer
Irvine or Andover
$108k-$173k/yr OnsiteFull Time
6+ YOEBachelor's in Electrical Engineering with 8+ years of related experience or Master's in Electrical Engineering with 6+ years of related experience; ASIC implementation, synthesis, DFT, floorplanning, place & route, clocking, power planning and analysis, timing closure, signal integrity, physical design checks.
EDA tools, Synthesis tools, Place and Route (P&R) tools, Floorplanning tools, Clocking/Timing analysis tools, Power analysis tools
3mo
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ASIC Design Engineer
Sunnyvale, California, United States
$120k-$243k/yr OnsiteFull Time
3+ YOEDesign ASICs using Verilog/SystemVerilog; strong digital design, timing, RTL, verification, and collaboration with cross-functional teams.
Verilog, SystemVerilog, EDA tools, Synthesis, Lint, Perl, Python
3mo
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ASIC Design Engineer IV
New York, New York, United States
$101k-$243k/yr RemoteFull Time
8+ YOESenior ASIC design engineer with 8-10 years hardware/EE/VHDL experience; secret clearance; Xilinx FPGA; Cadence Virtuoso; ModelSim/QuestaSim; VHDL/Verilog/SystemVerilog.
VHDL, Verilog, SystemVerilog, ModelSim, QuestaSim, Xilinx FPGA, Cadence Virtuoso, Synopsys, Genus
1mo
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Senior ASIC Verification Engineer
Austin, Texas, United States
$136k-$265k/yr HybridFull Time
5+ YOEBS/MS in Electrical or Computer Engineering (or equivalent), 5+ years design verification experience, UVM/SystemVerilog, ASIC flow, Perl or Python, familiarity with synthesis/simulation and debug tools.
SystemVerilog, UVM, Perl, Python, dc_shell, VCS, Debussy, GDB
3mo
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ASIC Test Engineer
Colorado Springs, Colorado, United States
$93k-$156k/yr OnsiteFull Time
5+ YOEBSEE or BSCS; 5+ years in ASIC testing; knowledge of 93K or similar test systems; strong programming and documentation skills; good communication; team-oriented; continuous improvement mindset; self-directed.
Programming, Documentation tools, Test systems (93K or similar)
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