1,159 asic engineer jobs at 196 companies in United States
1mo
Save
Mark Applied
Hide
ASIC Engineer, Architecture
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOE6+ years in ASIC/silicon engineering with experience in performance modeling; proficiency in C++ and Python; BS in CS/CE or equivalent; experience with SystemC, assembly, and ASIC performance analysis.
C++, Python, SystemC, CUDA, SystemVerilog, VHDL
4w
Save
Mark Applied
Hide
ASIC Engineer
New York City, New York, United States
$250k-$300k/yr OnsiteFull Time
4+ YOE4+ years RTL design and verification experience; ASIC design using Synopsys or Cadence flows; experience in front-end, back-end or verification; FPGA/ASIC familiarity; programming experience (Python, C++, Java, Haskell); willingness to learn OCaml.
Hardcaml, OCaml, Synopsys, Cadence, Python, C++, Java, Haskell
5d
Save
Mark Applied
Hide
ASIC Engineer
San Jose, California, United States
$155k-$223k/yr OnsiteFull Time
5+ YOEBachelor's degree and 5+ years, master's degree and 3+ years, or PhD with 0 years in ASIC design; requires Verilog/SystemVerilog, DFT/EDA tools, debugging, and scripting experience.
Python, Perl, Tcl, Shell, LSF, Verilog, SystemVerilog, Synopsys Design Constraints (SDC)
2w
Save
Mark Applied
Hide
ASIC Digital Design Engineer
Colorado Springs, Colorado, United States
$96k-$160k/yr OnsiteFull Time
0+ YOEBS in Electrical or Computer Engineering; 0–2 years designing and verifying digital or mixed-signal ASICs; ASIC/FPGA flows, DSP, RTL, object-oriented programming, and strong communication skills.
ASIC, DSP, RTL, FPGA
3w
Save
Mark Applied
Hide
ASIC Design Engineer
San Diego, California, United States
$99k-$148k/yr OnsiteFull Time
Bachelor's degree in a relevant technical field, ASIC, FPGA, or SoC design experience, digital design and architecture knowledge, industry-standard design tools, and Python, Tcl, Perl, or similar scripting experience.
Python, Tcl, Perl, RTL, FPGA, SoC, ASIC, IP, STA
1w
Save
Mark Applied
Hide
ASIC Design Engineer
Alameda, California, United States
$100k-$140k/yr OnsiteFull Time
Bachelor's in Electrical Engineering or Computer Science with ASIC industry experience, or Master's/PhD with hands-on ASIC experience. Requires analog and RTL design, programming, testing, debugging, communication, and Linux experience.
Linux, SPI, I2C, Cadence, Raspberry Pi, PDKs
1mo
Save
Mark Applied
Hide
Project Lead ASIC Engineer
Cambridge, Massachusetts, United States
$95k-$245k/yr HybridFull Time
5+ YOEBachelor's in engineering required (masters preferred); 5+ years ASIC hardware engineering experience with bachelor's (less with advanced degrees); ability to design/simulate transistor-level circuits, lead small teams, and work with fabrication/test sites.
1mo
Save
Mark Applied
Hide
Principal Engineer ASIC or Sr Principal Engineer ASIC
Manhattan Beach, California, United States
$125k-$235k/yr OnsiteFull Time
5+ YOESTEM degree with relevant years of experience, RTL design (VHDL/Verilog/SystemVerilog), ASIC/FPGA architecture, verification experience, lab testing, and ability to obtain a government security clearance.
VHDL, Verilog, SystemVerilog, Xilinx Vivado, Microchip Libero, UVM
2mo
Save
Mark Applied
Hide
ASIC Engineer, Annapurna Labs
Austin, Texas, United States
OnsiteFull Time
Bachelor's in Electrical Engineering (required); design and verification experience for ASICs/SoCs; strong SystemVerilog skills; experience debugging architectures and verifying IP-to-system levels; familiarity with microarchitecture, synthesis, timing, and RTL development.
SystemVerilog, Python, Perl, ARM
1mo
Save
Mark Applied
Hide
Principal Engineer ASIC or Sr Principal Engineer ASIC
Manhattan Beach, California, United States
$125k-$235k/yr OnsiteFull Time
5+ YOESTEM degree with 3–8+ years experience, RTL design (VHDL/Verilog) for space, ASIC/FPGA architecture, verification (SystemVerilog/UVM), lab testing, and ability to obtain/maintain government security clearance.
VHDL, Verilog, Xilinx Vivado, Microchip Libero, SystemVerilog, UVM, DSP
2w
Save
Mark Applied
Hide
ASIC Verification Engineer
Austin, Texas, United States
$116k-$190k/yr OnsiteFull Time
2+ YOEBS/MS in electrical or computer engineering or equivalent experience, 2+ years of design verification experience, pre-silicon verification with UVM/SystemVerilog, ASIC flows, Perl or Python, and strong debugging skills.
SystemVerilog, Universal Verification Methodology (UVM), Perl, Python, dc_shell, VCS, Debussy, GDB
2w
Save
Mark Applied
Hide
ASIC Production Engineer
San Jose, California, United States
$122k-$160k/yr OnsiteFull Time
8+ YOEMaster’s degree in electronics, electrical engineering, or related discipline; preferably 8+ years in ASIC production, test, and assembly; digital and analog electronics, statistical analysis, Six Sigma, Python or C++, and strong problem-solving skills.
Python, C++, Six Sigma, MIL-STD
1w
Save
Mark Applied
Hide
Senior ASIC Verification Engineer (PCIe/CXL)
San Jose or San Diego or Austin or Longmont
$146k-$250k/yr HybridFull Time
Expertise in ASIC verification, Verilog, SystemVerilog, UVM testbenches, and Python or Perl scripting; experience with PCIe, CXL, NVMe, or Ethernet; bachelor's or master's degree in computer or electrical engineering.
FPGA, ASIC, UVM, Verilog, SystemVerilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
5d
Save
Mark Applied
Hide
Senior ASIC Verification Engineer
Durham or Madison or Hillsboro
$168k-$311k/yr OnsiteFull Time
8+ YOEBachelor's or master's degree in electrical engineering, computer science, or computer engineering; 8+ years of relevant experience; SystemVerilog, C/C++, ASIC verification, coverage, and debugging expertise.
SystemVerilog, C, C++, VCS, IES, Debussy, GDB, Universal Verification Methodology (UVM), Perl, Python
5d
Save
Mark Applied
Hide
Senior ASIC Verification Engineer
Durham or Madison or Hillsboro
$168k-$311k/yr OnsiteFull Time
8+ YOEBachelor's or master's degree in electrical engineering, computer science, or computer engineering; 8+ years relevant experience; SystemVerilog, C/C++, ASIC verification, coverage, debugging, and simulation tools.
SystemVerilog, C, C++, VCS, IES, Debussy, GDB, Universal Verification Methodology (UVM), Perl, Python
2w
Save
Mark Applied
Hide
Senior ASIC Design Engineer
Boulder or Austin
$140k-$175k/yr HybridFull Time
5+ YOERequires a master's or PhD in electrical engineering or related field, 5+ years of hardware engineering experience, a complete ASIC cycle, DSP, RTL/SystemVerilog, FPGA, and EDA tool expertise.
SystemVerilog, RTL, FPGA, Cadence, Synopsys, Siemens EDA
2w
Save
Mark Applied
Hide
ASIC Verification Engineer
Roseville, California, United States
$120k-$243k/yr HybridFull Time
5+ YOERequires 5+ years of ASIC/SoC verification experience, SystemVerilog and UVM expertise, test planning, coverage analysis, assertions, randomization, and simulation-tool proficiency.
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Mentor Questa, Jenkins, UPF
3w
Save
Mark Applied
Hide
ASIC Verification Engineer
Sunnyvale, California, United States
$120k-$243k/yr HybridFull Time
3+ YOERequires 3+ years of ASIC/SoC verification experience, strong SystemVerilog and UVM expertise, and proficiency with test planning, coverage, assertions, randomization, and simulation debugging.
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Mentor Questa, Jenkins, UPF
3w
Save
Mark Applied
Hide
ASIC Verification Engineer
Sunnyvale, California, United States
$120k-$243k/yr HybridFull Time
3+ YOERequires 3+ years of ASIC/SoC verification experience, strong SystemVerilog and UVM expertise, and experience with test planning, coverage, assertions, simulation, and waveform debugging.
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Mentor Questa, Jenkins, UPF
4d
Save
Mark Applied
Hide
ASIC Verification Engineer
Irvine, California, United States
OnsiteFull Time
3+ YOEMSEE/CS for new graduates or BSEE/CS with 3+ years of ASIC design or verification experience; requires HDL proficiency, logic design, architecture, networking, and scripting skills.
SystemVerilog, UVM, Verilog, VHDL, C, C++, Python, Perl, TCL
Explore Jobs