2mo
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ASIC Engineer 2
Longmont, Colorado, United States
$143k-$176k/yr OnsiteFull Time
Define ASIC design/verification requirements; HDL/RTL, scripting; physical design basics; review requirements and collaborate with architects.
Perl, Python, C, Unix shell, Verilog, SystemVerilog, VHDL, RTL
3w
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Principal ASIC Design Engineer
Boulder or Austin
$180k-$220k/yr HybridFull Time
Atom Computing: Building scalable quantum computers using arrays of neutral atoms.
10+ YOEMS/PhD in EE, 10+ years post-degree hardware experience, 2+ full ASIC design cycles, FPGA-to-ASIC experience, SystemVerilog/RTL proficiency, DSP RTL experience, knowledge of Cadence/Synopsys/Siemens EDA, mixed-signal background, mentoring experience.
RTL, SystemVerilog, Cadence, Synopsys, Siemens EDA, FPGA
2mo
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ASIC Engineer 2
Longmont, Colorado, United States
$143k-$176k/yr OnsiteFull Time
Experience with Perl/Python/C/shell scripting, Verilog/System Verilog/VHDL, RTL design and verification, and physical design (layout, timing, power). Master's in ECE or related accepted.
Perl, Python, C, Unix shell, Verilog, System Verilog, VHDL
14h
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Senior Analog ASIC Design Engineer (Pipeline)
Beaverton or Boulder
$124k-$230k/yr HybridFull Time
5+ YOEMSEE/PhD or equivalent, 5+ years analog/mixed-signal IC design experience, proficiency in ASIC design, simulation and layout, strong analog/RF analysis, US Person required, limited domestic travel.
Ansys HFSS, Cadence EMX
1mo
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Senior Custom ASIC Engineering Lead
San Jose or Fort Collins or Irvine
$144k-$230k/yr OnsiteFull Time
10+ YOEExtensive ASIC physical design and STA experience, multiple tape-outs in advanced nodes, EDA tool and scripting (Tcl, shell) proficiency, knowledge of low-power design, and ability to manage customer ASIC programs. Bachelors+12 yrs or Masters+10 yrs required.
EDA, Tcl, Shell, Verilog
1mo
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ASIC/FPGA Design Engineer IV, TS/SCI Clearance
Boulder or King of Prussia or Littleton or Louisville or Sunnyvale
$124k-$246k/yr OnsiteFull Time
5+ YOEMust be US citizen with active Top Secret clearance, BS in Electrical Engineering or equivalent, 5+ years experience in ASIC/FPGA design/debug/verification, leadership and project management skills, and familiarity with project tools.
Microsoft Project, Microsoft Office, Atlassian JIRA, Earned Value Management System (EVMS)
1d
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ASIC Layout Designer
Boulder or Louisville or Beaverton
OnsiteFull Time
7+ YOEMinimum 7 years RF/analog/mixed-signal layout experience; proficient in broadband RF/high-speed layout, PDKs, floor planning, parasitic minimization, physical verification, and mentoring teams.
Cadence Virtuoso Schematic L, Layout L, Layout XL, Cadence Assura, PVS, Pegasus, Calibre, customIC, Solido, Aprisa, Questa, SVN, SOS, Synchronicity, IC Manage, Skill, Python, Ruby, Shell, Cadence Allegro PCB Design
1w
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Verification Engineer
San Jose or San Diego or Austin or Longmont
$124k-$213k/yr HybridFull Time
Experience in IP/ASIC/FPGA verification using UVM, Verilog/SystemVerilog, scripting (Python/Perl), and developing test plans and regression suites; bachelor’s or master’s in computer or electrical engineering.
UVM, Verilog, System Verilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
1w
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Staff FPGA Design Engineer
Berthoud, Colorado, United States
$150k-$180k/yr OnsiteFull Time
10+ YOEB.S. in Electrical Engineering with 10+ years in electronics hardware and ASIC/FPGA development for flight avionics; experience with mixed-signal design, VHDL/Verilog/SystemVerilog, timing closure, EMI/EMC, and hardware verification.
VHDL, Verilog, SystemVerilog, Python, TCL, Xilinx, Microsemi, MATLAB, Simulink, SPICE, Altium, SystemVerilog UVM, C, C++, assembly language, Linux/Windows shell scripting, Cocotb
2mo
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Design Verification (DV) Engineer
Austin or Boulder or Chicago or London or New York City
$175k-$250k/yr OnsiteFull Time
2+ YOE2+ years RTL verification for FPGA/ASIC; SystemVerilog/UVM; Python; Linux; Verilator; Cocotb; C++ is a plus.
SystemVerilog, UVM, Python, Verilator, Cocotb, Linux, C++
1mo
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SSD Architect
San Jose or Rancho Cordova or Longmont or Vancouver
$196k-$314k/yr HybridFull Time
5+ YOEBachelor's in computer engineering or computer science, 5+ years in embedded systems architecture with ASIC and/or firmware experience; SSD domain expertise, system-level architecture, and cross-functional leadership.
PCIe, NVMe, ASIC
2w
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
1mo
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Senior Site Technician - Bitcoin Mining
Cheyenne, Wyoming, United States
OnsiteFull Time
3+ YOE3+ years in Bitcoin mining site operations or similar high-density data environments; strong ASIC miner knowledge; electrical and low-voltage skills; networking basics; ability to read diagrams; excellent troubleshooting and communication; able to work outdoors and flexible shifts.
ASIC miners, networking equipment, PDUs, cooling systems, electrical distribution, diagnostics
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