41 asic engineer jobs at 14 companies in Berthoud, CO
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Analog ASIC Design Engineer
Boulder or Beaverton
$149k-$277k/yr OnsiteFull Time
5+ YOEBSEE/MSEE and 5+ years analog/mixed-signal IC design experience, proficiency with ASIC design tools, layout and RF analysis, strong communication, willingness to travel domestically, must be a U.S. Person.
Ansys HFSS, Cadence EMX
5d
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Analog ASIC Design Engineer
Boulder or Louisville or Beaverton
HybridFull Time
5+ YOEBSEE or MSEE in EE, 5+ years analog/mixed‑signal IC design experience, ASIC design and verification tool proficiency, RF and layout experience, lab characterization, strong communication and collaboration skills.
Ansys HFSS, Cadence EMX
2mo
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ASIC/FPGA Verification Engineer III
Denver or Highlands Ranch or King of Prussia or Sunnyvale
$101k-$178k/yr OnsiteFull Time
3+ YOEB.S. in Electrical Engineering or equivalent, 3+ years professional ASIC/FPGA verification experience, SystemVerilog and UVM/OVM/VMM proficiency, HDL and scripting experience, ability to obtain/maintain DoD Secret clearance (US citizenship required).
SystemVerilog, Universal Verification Methodology (UVM), OVM, VMM, VHDL, Verilog, Linux, Perl, TCL, Python
1mo
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Senior Custom ASIC Engineering Lead
San Jose or Fort Collins or Irvine
$144k-$230k/yr OnsiteFull Time
10+ YOEExtensive ASIC physical design and STA experience, multiple tape-outs in advanced nodes, EDA tool and scripting (Tcl, shell) proficiency, knowledge of low-power design, and ability to manage customer ASIC programs. Bachelors+12 yrs or Masters+10 yrs required.
EDA, Tcl, Shell, Verilog
2mo
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Principal Engineer, Firmware
Longmont, Colorado, United States
$161k-$275k/yr OnsiteFull Time
7+ YOEBachelor's in CE/EE/CS or related, 7+ years firmware development experience, proficiency in machine/assembly/C/C++/Python, ASIC/FPGA bring-up, system-level debug, and cross-team architectural leadership.
machine language, assembly language, C, C++, Python, FTL, NVMe, PCIe, ASIC, FPGA
3w
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Verification Engineer
San Jose or San Diego or Austin or Longmont
$124k-$213k/yr HybridFull Time
Experience in IP/ASIC/FPGA verification using UVM, Verilog/SystemVerilog, scripting (Python/Perl), and developing test plans and regression suites; bachelor’s or master’s in computer or electrical engineering.
UVM, Verilog, System Verilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
5d
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Hardware Engineer
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$91k-$113k/yr OnsiteFull Time
Early-career candidates pursuing or recently completing an engineering degree; familiarity with hardware, firmware, ASIC/SoC, or systems; programming and design experience through coursework or projects; strong analytical and communication skills.
Verilog/SystemVerilog, RTL, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, Git, Linux, IDE, CAD, Microsoft Office, RTOS
2mo
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Principal Engineer, Firmware
Longmont, Colorado, United States
$161k-$275k/yr OnsiteFull Time
7+ YOELead firmware architecture for SSDs; 7+ years embedded firmware; C/C++, Python; ASIC/FPGA bring-up; strong communication.
C, C++, Python
3w
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Staff FPGA Design Engineer
Berthoud, Colorado, United States
$150k-$180k/yr OnsiteFull Time
10+ YOEB.S. in Electrical Engineering with 10+ years in electronics hardware and ASIC/FPGA development for flight avionics; experience with mixed-signal design, VHDL/Verilog/SystemVerilog, timing closure, EMI/EMC, and hardware verification.
VHDL, Verilog, SystemVerilog, Python, TCL, Xilinx, Microsemi, MATLAB, Simulink, SPICE, Altium, SystemVerilog UVM, C, C++, assembly language, Linux/Windows shell scripting, Cocotb
3w
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Space Electrical Chief Engineer
Englewood, Colorado, United States
$141k-$252k/yr OnsiteFull Time
13+ YOEExtensive spacecraft electrical experience (system architecture, power, avionics, EEE parts), ability to obtain DoD clearance, 13+ years engineering experience (or equivalent), leadership of multidisciplinary teams, requirements and test oversight.
DOORS, SpaceWire, CAN, MIL STD 1553, Ethernet, FPGA, ASIC, HIL, EMC, EMI, MBSE, MIL STD 1540, MIL STD 461, NASA GEVS
1mo
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Engineer II - FPGA Verification
Westminster, Colorado, United States
$79k-$135k/yr OnsiteFull Time
2+ YOEBS in Engineering +2 years experience (Master's/PhD may substitute), FPGA/ASIC verification experience, SystemVerilog and UVM proficiency, object-oriented testbench design, coverage-driven verification, and eligibility to obtain Secret clearance; U.S. person required.
System Verilog, UVM, Modelsim, Questa, C++, Windows, Linux, Ruby, Python, TCL
1mo
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Principal Electrical Engineer - Denver, CO
Denver, Colorado, United States
$130k-$209k/yr HybridFull Time
12+ YOEB.S. in Electrical Engineering, 12+ years designing complex electrical systems, system architecture experience, technical leadership and mentorship, mixed-signal/analog/digital expertise; medical device or regulated industry experience preferred.
FPGA, ASIC, HDL
4w
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SLD Avionics FPGA Engineer III - Lunar Permanence
Seattle or Denver
$120k-$183k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
5+ YOEBachelor's/Master's in engineering or related field,5+ years FPGA/ASIC design and verification,RTL in Verilog/SystemVerilog/VHDL,FPGA tools and simulators,UVM/OVM testbenches,ability to travel ~10%,U.S. work authorization required.
Verilog, SystemVerilog, VHDL, Xilinx Vivado, Intel Quartus, Lattice Diamond, Radiant, Microchip Libero, ModelSim, QuestaSim, Perl, Python, Tcl, Git, SVN, AMBA, AXI, AHB, APB, IEEE 802.3, XAUI, JESD204, I2C, SPI, UVM, OVM
2d
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Pre-Silicon Diagnostics Engineer
Arizona or Bloomington or Fort Collins
$106k-$243k/yr RemoteFull Time
4+ YOEDevelop diagnostics and emulator-based validation for ASICs, proficient in Python,OOP,Linux,knowledge of high-speed networking;4+ years experience;strong written and verbal English.
Python, Linux, UVM, Verilog, SystemVerilog
2d
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Pre-Silicon Diagnostics Engineer
Arizona or Bloomington or Fort Collins
$106k-$243k/yr RemoteFull Time
4+ YOE4+ years experience in diagnostics/validation/firmware/embedded software for ASICs; proficiency in object-oriented programming, Python, Linux; strong debugging, networking fundamentals, and communication skills.
Python, Linux, UVM, Verilog, SystemVerilog
2d
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Pre-Silicon Diagnostics Engineer
Arizona or Bloomington or Fort Collins
$106k-$243k/yr RemoteFull Time
4+ YOEExperience in diagnostics/validation/firmware/embedded software for ASICs, 4+ years experience, proficiency in object-oriented programming, Python, Linux, networking fundamentals, strong debug and communication skills.
Python, Linux, UVM, Verilog, SystemVerilog
1mo
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Senior FPGA Verification Engineer - $30K Sign On Bonus
Westminster, Colorado, United States
$97k-$165k/yr HybridFull Time
4+ YOEBS in engineering plus 4+ years related experience (or equivalent), strong FPGA/ASIC verification skills with System Verilog and UVM, coverage-driven verification, class-based constrained-random testbenches, and strong communication skills; eligible for U.S. security clearance.
System Verilog, UVM, Modelsim, Questa, C++, Windows, Linux, Ruby, Python, TCL
1mo
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SSD Architect
San Jose or Rancho Cordova or Longmont or Vancouver
$196k-$314k/yr HybridFull Time
5+ YOEBachelor's in computer engineering or computer science, 5+ years in embedded systems architecture with ASIC and/or firmware experience; SSD domain expertise, system-level architecture, and cross-functional leadership.
PCIe, NVMe, ASIC
4w
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
4w
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Applications Engineer - FPGA Prototyping
San Diego or Fremont or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville
$167k-$334k/yr HybridFull Time
5+ YOE5+ years experience in chip/system design, verification, simulation or prototyping; BS/MS in EE/CE/CS; expertise with SystemVerilog/Verilog/VHDL, FPGA/ASIC implementation, scripting (Perl, Python), and FPGA tools (Vivado, Quartus).
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, Makefiles, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
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