51 asic engineer jobs at 20 companies in Bridgewater, MA
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Project Lead ASIC Engineer
Cambridge, Massachusetts, United States
$95k-$245k/yr HybridFull Time
5+ YOEBachelor's in engineering required (masters preferred); 5+ years ASIC hardware engineering experience with bachelor's (less with advanced degrees); ability to design/simulate transistor-level circuits, lead small teams, and work with fabrication/test sites.
3mo
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ASIC Physical Design Engineer
Maynard or Austin
$136k-$195k/yr HybridFull Time
5+ YOEBachelors in Engineering with 5+ years or Masters in Engineering with 3+ years in ASIC physical design; experience with floorplanning, place-and-route, STA, timing closure, DFT collaboration, scripting, and design flow optimization.
Cadence Innovus, Synopsys ICC2, Synopsys DC/FC, Synopsys Formality, Cadence LEC, Tempus, Python, TCL, Perl
3w
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Sr. ASIC Design Engineer, Blink/Ring ASIC Team
North Reading, Massachusetts, United States
$159k-$215k/yr OnsiteFull Time
Bachelor's in Electrical Engineering, knowledge of UVM and Matlab, experience delivering products to volume production, low-power design expertise, RTL coding and debug, and leadership in technical initiatives.
UVM, Matlab, RTL
2mo
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Senior ASIC Front End Infrastructure Engineer
Santa Clara or Westford or Austin or Durham
$184k-$357k/yr OnsiteFull Time
8+ YOE8+ years experience; Masters in Electrical Engineering, Computer Engineering, Computer Science or related; Python/Perl; AI tooling; Make; CI (Jenkins); strong problem solving; ASIC/CPU verification knowledge.
Python, Perl, Make, Jenkins
2mo
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Staff Engineer, Digital ASIC Design (CONTRACT)
Burlington or New York
HybridContract
8+ YOEBS/MS/PhD in EE/CE; 8+ yrs in digital IC/ASIC/SoC; RTL ownership; SystemVerilog/Verilog; high-throughput datapaths; silicon constraints; SV/UVM; Python/cocotb; post-silicon bring-up.
SystemVerilog/Verilog, UVM, Python, cocotb, RTL, RTL verification, Fixed-point modeling
2mo
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Senior ASIC Timing Engineer
Westford or Durham
$168k-$311k/yr OnsiteFull Time
4+ YOEBS in ECE (8+ yrs) or MS (4+ yrs) in synthesis and timing; hands-on STA, timing constraints, ECOs, physical design and synthesis/LEC; experience with Synopsys PrimeTime or Cadence Tempus; Python, Tcl, Make scripting.
Synopsys PrimeTime, Cadence Tempus, Python, Tcl, Make
3mo
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Mixed Signal ASIC Engineer
Boston, Massachusetts, United States
OnsiteFull Time
5+ YOEPhD in electrical engineering or equivalent industry experience; 5+ years designing analog/mixed-signal ICs; strong ADC/DAC, amplifiers; tape-out experience; Cadence or Synopsys tools; end-to-end IC development.
Cadence, Synopsys
2mo
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ASIC Design Verification Engineer
Irvine or Andover or Broomfield
$129k-$207k/yr OnsiteFull Time
3+ YOEConstrained-random design verification experience using System Verilog/UVM, coverage-driven methodologies, experience with VCS/Incisive and scripting (Python/Perl). Degree with significant related experience required (varies by degree).
System Verilog, UVM, VCS, Incisive, Python, Perl
2w
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ASIC/FPGA Methodology Engineer (TERADYNE, North Reading, MA)
North Reading, Massachusetts, United States
$155k-$248k/yr OnsiteFull Time
3+ YOEBachelor's or master's degree in electrical or computer engineering, 3+ years of FPGA and embedded design experience, and proficiency with design, verification, CI/CD, and Linux tools.
Verilog, Vivado, Quartus, Jenkins, Docker, Git, Linux, LSF, ClearCase, Artifactory, SystemVerilog, UVM
2mo
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Senior Principal Engineer, Architecture ASIC / System
Toronto or Ottawa or Burlington or Irvine or Morrisville or Santa Clara or Westborough
$192k-$255k/yr OnsiteFull Time
14+ YOESenior architect with 14+ years in system architecture for SoC; expertise in interconnects, memory hierarchies, power management, security; strong technical leadership.
IP evaluation, IP block, SoC architecture
3w
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Senior Engineer, Physical Design Engineering (ASIC)
Somerset County or Wilmington
$117k-$161k/yr OnsiteFull Time
5+ YOEExpertise in ASIC/SoC physical design, floorplanning, P&R, timing closure, physical verification, scripting (TCL/Python), and cross-functional collaboration; 5+ years experience preferred.
Cadence, TCL, Python
1w
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Application Engineer, Sr. Staff-18390
Sunnyvale or Texas or Boxborough or Ottawa
$157k-$235k/yr OnsiteFull Time
8+ YOERequires 8+ years in Memory Interface or other Interface IP, hands-on lab debug and silicon bring-up, Linux, Verilog/VHDL, ASIC flows, and a bachelor's or master's degree in Electronics Engineering.
Linux, Verilog, VHDL, ASIC, HBM, DDR, LPDDR, PCIe, Ethernet, UCIe, AMBA, AXI, DDR5, LPDDR6, MRDIMM2, HBM4
1mo
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Senior Electrical Engineer
Wilmington, Massachusetts, United States
$115k-$173k/yr OnsiteFull Time
5+ YOEBS/MS in Electrical Engineering, 5+ years product development experience, motion control required, embedded microprocessors, PCB layout (Altium) experience, firmware/FPGA/Verilog knowledge, ability to support system-level design and testing.
PCB Layout Tools, Altium, PLD, FPGA, ASIC, Verilog
3mo
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Staff Design Verification Engineer – Coherent Interconnect
Boston or Austin
OnsiteFull Time
7+ YOEBS/ MS in Electrical/Computer Engineering; 7+ years ASIC/SoC verification; strong CXL/CHI/AXI; SystemVerilog/UVM; cache-coherent systems; test plans, coverage; Python scripting.
SystemVerilog, UVM, Python
1mo
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Electrical Engineer - Hardware & Embedded Systems
Waltham, Massachusetts, United States
$100k-$116k/yr OnsiteFull Time
4+ YOEBachelor's in electrical/computer engineering, 4+ years relevant experience, 3+ years embedded systems, proficiency in Embedded C/C++, RTOS, hardware-software integration, control systems, and communication protocols (I2C, SPI, UART, CAN).
Embedded C/C++, RTOS, I2C, SPI, UART, CAN, MATLAB/Simulink, LabVIEW, PLCs, FPGA, ASIC, Git, IDEs, debuggers
3w
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Sr. Design for Test (DFT) Engineer
Toronto or Mountain View or Boston
HybridFull Time
13+ YOEBachelor's in Electrical Engineering, 13+ years DFT experience on ASICs, 2+ tapeouts, experience with DFT CAD/ATPG, Python/TCL scripting, post-silicon bring-up and ATE interfacing.
Python, TCL, SystemVerilog, ATPG, ATE
1w
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MTS Silicon Design Engineer
Boxborough, Massachusetts, United States
OnsiteFull Time
3+ YOEMaster's degree and 3 years of related engineering experience, or bachelor's degree and 5 years. Requires hardware verification, Verilog/SystemVerilog/VHDL, UVM/AVM, C/C++/Python, CPU/GPU/SoC architecture, and pre-silicon verification.
Verilog, SystemVerilog, VHDL, UVM, AVM, C, C++, Python, CPU, GPU, SoC, ASIC, RTL
2mo
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FPGA Design Engineer II
Needham, Massachusetts, United States
$129k-$166k/yr OnsiteFull Time
3+ YOEBS/MS in related field, 3+ years FPGA/ASIC digital logic design, proficiency in SystemVerilog or VHDL, experience with simulation/debug tools (VCS, Verdi), Linux, strong debugging and communication skills.
SystemVerilog, VHDL, VCS, Verdi, Linux, C, Python, Perl, PCIe, Ethernet, DDR
1mo
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Engineer: Sr. Electrical Design Engineer
Cambridge, Massachusetts, United States
$80k-$110k/yr OnsiteFull Time
5+ YOEMaster's in EE, 5+ years product development experience, PCB and embedded hardware design, Altium/Eagle, C/Assembly, verification/validation, FDA/ISO 13485 experience, LabVIEW/MATLAB/Simulink familiarity.
Altium, Autodesk Eagle, C, Assembly, Verilog, VHDL, FPGA, ASIC, LabVIEW, MATLAB, Simulink, Java, Android, oscilloscopes, logic analyzers
2d
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Quantum Systems Architect
Delft or Boston
HybridFull Time
8+ YOEMaster’s or Ph.D. in a technical discipline; 8+ years in system architecture, including 2+ years in quantum control or RF test and measurement. Requires FPGA, real-time, mixed-signal, systems engineering, modeling, and cross-domain expertise.
quantum compiler, FPGA, ASIC, System-on-Chip (SoC), AWG, ADC, DAC, PLL
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