30 asic engineer jobs at 6 companies in Carrboro, NC
2mo
Save
Mark Applied
Hide
Senior ASIC Verification Engineer
Durham or Madison or Hillsboro
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelor's or Master's in EE/CS/CE (or equivalent), 5+ years ASIC verification experience, strong SystemVerilog and C/C++ skills, UVM, constrained-random and coverage-driven verification, familiarity with VCS/IES and debug tools.
SystemVerilog, C, C++, Universal Verification Methodology (UVM), VCS, IES, Debussy, GDB, Semiformal Verification (SFV), Perl, Python
1mo
Save
Mark Applied
Hide
Senior ASIC Design Engineer - Agentic AI
Santa Clara or Austin or Durham
$168k-$311k/yr OnsiteFull Time
8+ YOEMaster's/PhD or equivalent experience, 8+ years experience, micro-architecture and RTL (Verilog) expertise, ASIC design flow knowledge, Python prototyping, experience with LLM fine-tuning, RAG pipelines, and vector databases.
Verilog, Python, RAG pipelines, vector databases, large language models
3d
Save
Mark Applied
Hide
Principal Engineer SOC/ASIC Design
Raleigh, North Carolina, United States
$173k-$259k/yr OnsiteFull Time
8+ YOEBachelor's degree and 8+ years, master's and 7+ years, or PhD and 6+ years in ASIC design, verification, validation, integration, or related work; preferred architecture, scripting, DV, leadership, and financial experience.
System-In-Package (SIP)
2mo
Save
Mark Applied
Hide
Senior Principal Engineer, Architecture ASIC / System
Toronto or Ottawa or Burlington or Irvine or Morrisville or Santa Clara or Westborough
$192k-$255k/yr OnsiteFull Time
14+ YOESenior architect with 14+ years in system architecture for SoC; expertise in interconnects, memory hierarchies, power management, security; strong technical leadership.
IP evaluation, IP block, SoC architecture
1mo
Save
Mark Applied
Hide
Senior ASIC Physical Design Engineering Technical Lead
San Jose or Austin or Research Triangle Park
$211k-$305k/yr HybridFull Time
5+ YOEAdvanced degree in Electrical Engineering with significant physical design experience (BSc+12y / MSc+8y / PhD+5y), RTL-to-GDSII/tapeout experience at 7nm/5nm/3nm, EDA tool proficiency, UPF low-power methods, Python and AI tools experience.
Innovus, Tempus/Primetime, Redhawk/Voltus, Calibre/Pegasus, UPF, Python, RTL2GDSII, Flex-HTree, AI tools
2mo
Save
Mark Applied
Hide
Staff Engineer - Digital ASIC and Signal Processing Chip Architect/Systems Engineer
Durham, North Carolina, United States
$131k-$190k/yr OnsiteFull Time
10+ YOE10+ years of experience, including 5 years in digital IC design; expertise in digital signal processing, RTL design, digital architecture; firmware and embedded software; radio architecture; microprocessor subsystems; experience across hardware-software co-design.
SystemVerilog, MATLAB, Python, DSP cores
1mo
Save
Mark Applied
Hide
DFT Engineer (CE-64000920)
Austin or Chandler or Greensboro
HybridFull Time
2+ YOEMSEE with 2+ years or BS with relevant experience; hands-on ASIC DFT design and verification; experience with FastScan, TestKompress, TetraMAX, Test Compiler; MBIST, scan/ATPG, Verilog/SystemVerilog/VHDL; scripting (Perl, Python, TCL); strong communication.
FastScan, TestKompress, TetraMAX, Test Compiler, Verilog, SystemVerilog, VHDL, Perl, Python, TCL
Explore Jobs