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Principal Engineer, ASIC Physical Design
Minneapolis, Minnesota, United States
OnsiteFull Time
15+ YOE15+ years ASIC physical design experience, bachelor's or master's in EE/electronics/computer architecture, production tape-outs, UPF/CPF low-power expertise, scripting in Tcl/Perl/Python, Synopsys/Cadence/Calibre experience.
Synopsys, Cadence, Calibre, Tcl, Perl, Python, UPF, CPF
4d
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ASIC FPGA Engineer (New Hire Sign On Bonus Eligible)
Bloomington, Minnesota, United States
$114k-$121k/yr OnsiteFull Time
2+ YOEBachelor in Electrical/Computer Engineering (or related) plus 2 years experience (or Master plus 6 months); ability to obtain DoD Secret clearance; U.S. citizenship required; SystemVerilog preferred; Microsoft Office and ASIC/FPGA tool experience.
Microsoft Office, System Verilog, FPGA
1mo
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Engineer, ASIC Physical Design
Minneapolis, Minnesota, United States
$143k-$176k/yr FieldFull Time
Experience with chip floor-planning, placement and routing, power/clock routing, static timing analysis (Tempus or PrimeTime), place-and-route (Innovus, ICC2, Fusion Compiler), physical verification (Calibre, IC Validator, Hercules), and scripting with Tcl/Cshell. Master's in EE/CE or related accepted.
Tempus, PrimeTime, Innovus, ICC2, Fusion Compiler, Calibre, IC Validator, Hercules, Tcl, Cshell
1mo
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Senior ASIC Design Verification Engineer
Minneapolis, Minnesota, United States
OnsiteFull Time
3+ YOE3+ years IP/SoC verification; UVM, SystemVerilog, Python; Bachelor's or Master's in Electrical/Computer Engineering.
UVM, SystemVerilog, Python
1mo
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Senior ASIC Design Verification Engineer
Minneapolis, Minnesota, United States
OnsiteFull Time
3+ YOEBachelor's degree in EE/CE, 3+ years IP/SoC verification experience, hands-on UVM/SystemVerilog and Python, constrained-random verification, strong debugging and communication skills.
UVM, SystemVerilog, Python
1mo
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Senior ASIC Design Verification Engineer
Minneapolis, Minnesota, United States
OnsiteFull Time
3+ YOEBachelor's or Master's in EE/CE, 3+ years IP/SoC verification experience, hands-on UVM, constrained-random verification, strong SystemVerilog and Python skills, analytical debugging and communication abilities.
UVM, SystemVerilog, Python
1mo
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Senior ASIC Design Verification Engineer
Minneapolis, Minnesota, United States
OnsiteFull Time
3+ YOE3+ years IP/SoC verification; UVM; SystemVerilog; Python; strong debugging and communication skills.
SystemVerilog, Python, UVM, Constrained-Random Verification, Python-based testbenches
2mo
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Principal Engineer, ASIC Physical Design
Minneapolis, Minnesota, United States
OnsiteFull Time
15+ YOE15+ years hands-on ASIC physical design; BA/MA in EE/ Electronics/ Computer Architecture; multiple production tape-outs; strong low-power techniques; scripting (Tcl/Perl/Python).
Synopsys, Cadence, Calibre, UPF/CPF, Tcl, Perl, Python
1mo
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Engineer, ASIC Physical Design
Minneapolis, Minnesota, United States
$143k-$176k/yr HybridFull Time
Master's degree in Electrical or Computer Engineering; floorplanning/placement/routing; timing analysis; Cadence/Synopsys tools; Mentor IC Validator; Tcl/Cshell; design and verification collaboration.
Cadence Innovus, Cadence Tempus, Synopsys ICC2, Synopsys Fusion Compiler, Synopsys Primetime, Mentor Calibre, IC Validator, Hercules, Tcl, Cshell
4d
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FPGA Engineer
Bloomington, Minnesota, United States
$99k-$107k/yr OnsiteFull Time
1+ YOEBachelor's in Electrical/Computer Engineering (or related) plus 1 year, or Master's; US citizenship and ability to obtain DoD Secret clearance; experience in ASIC/FPGA design, simulation, verification, and documentation; EM simulation/synthesis knowledge; Microsoft Office skills.
ASIC, FPGA, Microsoft Office
2w
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Lead Certification AEH Engineer
Minneapolis or Phoenix or Clearwater
$140k-$175k/yr HybridFull Time
5+ YOEBachelor's in Engineering/Aerospace, 5+ years ASIC/FPGA HDL design/verification or AEH certification liaison experience, US person required, familiarity with FAA regulations and certification processes preferred.
1mo
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Lead MEMS Systems Engineer
Plymouth or Minneapolis
$135k-$160k/yr HybridFull Time
10+ YOEMaster's in engineering, 10+ years MEMS/ASIC or analog electronics experience, proficiency with Pro/ENGINEER/CREO, ANSYS/Siemens NX/COMSOL/FEMTools, LabVIEW, and experience designing low-noise analog front ends; U.S. status required.
Pro/ENGINEER, CREO, ANSYS, Siemens NX, COMSOL, FEMTools, LabVIEW, Siemens L-Edit MEMS, Electronic Design Automation (EDA) Tools, PSPICE, QSPICE, SPICE, LTspice, TINA
1mo
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Senior Electrical Engineer, Battery & Power
Arden Hills, Minnesota, United States
$85k-$162k/yr OnsiteFull Time
5+ YOEBachelor's in electrical engineering, 5+ years experience with battery/power systems, specification development, root cause analysis in regulated environments, cross-functional collaboration, and strong power-electronics knowledge.
ASIC
1w
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FPGA Engineer (New Hire Bonus Eligible)
Bloomington, Minnesota, United States
$117k-$1127k/yr OnsiteFull Time
2+ YOEBachelor's in Electrical/Computer Engineering required (or Master's with reduced experience), 2+ years relevant experience, US citizenship, ability to obtain DoD Secret clearance, ASIC/FPGA design and verification experience, Microchip PolarFire, UVM, SystemVerilog, Microsoft Office.
Microchip Polarfire, UVM, SystemVerilog, Microsoft Office
1mo
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Senior Electrical Engineer, Battery & Power
Arden Hills, Minnesota, United States
$85k-$162k/yr OnsiteFull Time
5+ YOEBachelor's in electrical engineering, 5+ years experience in battery/power systems, specification development, root cause analysis in regulated/high-reliability environments, cross-functional collaboration, and knowledge of power electronics and battery modeling.
ASIC, ISO 14708, IEC 60601, fault tree analysis, DOE, statistical analysis
2mo
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Principal Digital Design Engineer / Chip Lead
Minneapolis or Boise or Folsom or Richardson or San Jose
$206k-$410k/yr OnsiteFull Time
10+ YOE10+ years in digital/ASIC design with chip/design lead ownership; SystemVerilog RTL; synthesis/timing tools; cross-team integration leadership.
SystemVerilog, DC, Genus, PrimeTime, Tempus
2mo
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DMTS Digital Design Engineer / Chip Lead
Minneapolis or Boise or Folsom or Richardson or San Jose
$206k-$410k/yr OnsiteFull Time
10+ YOE10+ years ASIC/digital design experience with prior tape-out; BS/MS/PhD in EE/CE or related; expert SystemVerilog; synthesis (Design Compiler/Genus), static timing analysis (PrimeTime/Tempus), RTL simulation (VCS/Xcelium), CDC tools; chip architecture and IP integration experience.
SystemVerilog, Synopsys Design Compiler, Cadence Genus, PrimeTime, Tempus, VCS, Xcelium, Verdi, DVE, SpyGlass, JasperGold
3mo
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Senior Digital Mixed-Signal (DMS) Verification Engineer
Mendota Heights or Broomfield
$108k-$173k/yr OnsiteFull Time
5+ YOE5+ years in digital verification of mixed-signal ASICs/SoCs; UVM/OVM; analog/digital boundary expertise; leadership; Bachelors in EE/CE/CS with 8+ yrs experience or Masters with 6+ yrs; English communication.
UVM, OVM, SystemVerilog, SystemVerilog Assertions, scripting, automation tooling
2mo
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Sr Engineer – Network Operating Systems
Brooklyn Park, Minnesota, United States
$98k-$176k/yr HybridFull Time
5+ YOE4-year degree or equivalent; 5+ years software development; strong C/C++; Linux; Python; Docker; networking; I2C; hardware/embedded; Agile/Scrum.
C, C++, Python, Shell, Git, Make, Docker, Linux, Systemd, Build Tools, Packages, TLS, DNS, BGP, LACP, LLDP, VLANs, I2C, Networking, ASIC, Memory-mapped I/O
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