3 asic engineer jobs at 1 company in Cicero, IN
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Principal Engineer - FPGA/ASIC Design
Indianapolis or West Lafayette
$113k-$184k/yr HybridFull Time
3+ YOEU.S. citizen with degree in electronics/computer engineering and 3+ years experience (or higher degree), expertise in FPGA/ASIC design (VHDL/Verilog/SystemVerilog), DO-254 verification, timing closure, synthesis, testbenches, lab validation, and scripting (TCL/Python/Shell).
VHDL, Verilog, SystemVerilog, DO-254, TCL, Python, Shell, Windows, Linux, Git, SVN, Actel, Xilinx, MATLAB, Simulink, Cameo Systems Modeler (MagicDraw), ILA, JTAG, oscilloscopes, logic analyzers
3w
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Principal Engineer - FPGA/ASIC Design
Indianapolis or West Lafayette
$113k-$184k/yr HybridFull Time
3+ YOEDesign, verify, integrate and test FPGA/ASIC solutions; develop RTL (VHDL/Verilog/SystemVerilog); achieve timing closure; lab validation; scripting and version control experience; U.S. citizenship required.
VHDL, Verilog, SystemVerilog, ILA, JTAG, TCL, Python, Shell, Git, SVN, Actel, Xilinx, MATLAB, Simulink, Cameo Systems Modeler (MagicDraw), Windows, Linux
1d
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Principal Engineer - FPGA/ASIC Design
Reston or Washington, D.C. or Indianapolis or West Lafayette
$152k-$247k/yr HybridFull Time
5+ YOEBachelor's with 5+ years, master's with 3+ years, or PhD in electronics or computer engineering; U.S. citizenship required. FPGA/ASIC, RTL, VHDL/Verilog/SystemVerilog and verification experience required.
FPGA, ASIC, DO-254, VHDL, Verilog, SystemVerilog, TCL, Python, Shell, Windows, Linux, Git, SVN, Actel, Xilinx, MATLAB, Simulink, Cameo Systems Modeler, MagicDraw, SysML, ILA, JTAG, Microsoft Excel