1mo
Save
Mark Applied
Hide
Senior ASIC Physical Design Engineer
San Jose or Austin or Research Triangle Park
$165k-$241k/yr OnsiteFull Time
1+ YOEDegree in Electrical or Computer Engineering with relevant ASIC experience (varies by degree), experience with EDA tools (Innovus, Tempus, PrimeTime, Redhawk, Voltus, Calibre, Pegasus), STA experience, and Python scripting.
Innovus, Tempus, PrimeTime, Redhawk, Voltus, Calibre, Pegasus, Tweaker, Static Timing Analysis (STA), Python, AI tools
1mo
Save
Mark Applied
Hide
Senior Principal Engineer, Architecture ASIC / System
Toronto or Ottawa or Burlington or Irvine or Morrisville or Santa Clara or Westborough
$192k-$255k/yr OnsiteFull Time
14+ YOESenior architect with 14+ years in system architecture for SoC; expertise in interconnects, memory hierarchies, power management, security; strong technical leadership.
IP evaluation, IP block, SoC architecture
3w
Save
Mark Applied
Hide
ASIC Physical Design Technical Lead
San Jose or Austin or Research Triangle Park
$184k-$264k/yr OnsiteFull Time
3+ YOEBachelor's+8 yrs, Master's+6 yrs, or PhD+3 yrs in Electrical Engineering with physical design experience; RTL-to-GDSII tapeout experience in 7nm/5nm/3nm; experience with EDA tools and low-power (UPF).
Innovus, Tempus, PrimeTime, Redhawk, Voltus, Calibre, Pegasus, UPF, Python
3w
Save
Mark Applied
Hide
Senior ASIC Physical Design Engineering Technical Lead
San Jose or Austin or Research Triangle Park
$211k-$305k/yr HybridFull Time
5+ YOEAdvanced degree in Electrical Engineering with significant physical design experience (BSc+12y / MSc+8y / PhD+5y), RTL-to-GDSII/tapeout experience at 7nm/5nm/3nm, EDA tool proficiency, UPF low-power methods, Python and AI tools experience.
Innovus, Tempus/Primetime, Redhawk/Voltus, Calibre/Pegasus, UPF, Python, RTL2GDSII, Flex-HTree, AI tools
4w
Save
Mark Applied
Hide
ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead (Remote)
San Jose or Research Triangle Park or Acton or Dallas or Tempe or Cary or Carlsbad or Colorado Springs
$184k-$264k/yr RemoteFull Time
3+ YOEBachelor's/MS/PhD in Electrical Engineering with 3+ to 8+ years SI/PI experience; expertise in high-speed design, SI/PI simulation, layout review, SPICE; mentoring and leadership experience.
Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, Ansys EM, SPICE, Vector Network Analysis, IBIS
1mo
Save
Mark Applied
Hide
ASIC Physical Design Technical Lead
San Jose or Austin or Research Triangle Park
$184k-$264k/yr OnsiteFull Time
3+ YOEBachelor/Master/PhD in Electrical Engineering with 3+–8+ years physical design experience; RTL-to-GDSII tapeout experience at advanced nodes; experience with Innovus, Tempus/Primetime, Redhawk/Voltus, Calibre/Pegasus, UPF, and Python.
Innovus, Tempus, Primetime, Redhawk, Voltus, Calibre, Pegasus, Python, UPF
1w
Save
Mark Applied
Hide
Principal Physical Design Engineer
Mountain View or Raleigh or Austin
$143k-$275k/yr HybridFull Time
3+ YOEAdvanced degree or equivalent experience in EE/CE/CS with substantial physical design/ASIC implementation experience, ability to pass Microsoft security screening and export-control eligibility.
5d
Save
Mark Applied
Hide
Software Engineer
Research Triangle Park, North Carolina, United States
$127k-$182k/yr OnsiteFull Time
5+ YOEBachelor's+5yrs or Master's+3yrs (or PhD), strong C++ and Python skills, SDLC experience, embedded/ASIC software development, networking knowledge, excellent troubleshooting and communication.
C++, Python, Silicon SDK, SONiC, FBOSS, SAI
3mo
Save
Mark Applied
Hide
Principal SOC Architect, AI Accelerators (Multiple Locations
San Diego or Hillsboro or Santa Clara or Austin or Raleigh
$173k-$305k/yr OnsiteFull Time
6+ YOEAdvanced degree in engineering, 6+ years ASIC/SoC experience (or equivalent combinations), 3+ years datacenter product experience, deep knowledge of datacenter security, RAS, virtualization, telemetry, power/cooling and server architectures.
PCIe, SRIOV, SIOV, IDE, TDISP, Ethernet, Confidential Compute