2mo
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Senior Principal ASIC FPGA Engineer
Boise or United States
$191k-$212k/yr RemoteFull Time
8+ YOEBachelor's in Electrical/Computer Engineering or related field with 10+ years, or Master's with 8+ years; DoD Secret clearance; U.S. citizenship.
Verilog, SystemVerilog, VHDL, ASIC/FPGA design tools
2mo
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HIG Product Engineer - Media Health
Boise, Idaho, United States
OnsiteFull Time
Master's degree or equivalent in Computer/Electrical Engineering, experience in digital circuit design, ASIC testing, Python and C programming, BIST APG programming, Linux, and hands-on bench testing for memory products.
Probe, ATE, Python, C, BIST APG, Linux, JMP, SPICE, Verilog, ASIC
2mo
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HIG Product Engineer - Media Health
Boise, Idaho, United States
OnsiteFull Time
Master's in Computer or Electrical Engineering or related field; digital circuit design, ASIC testing with scan tools, Python and C; Linux; bench testing; BIST/APG memory testing.
Python, C, Linux, Verilog, SPICE, JMP
2mo
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Principal Digital Design Engineer / Chip Lead
Minneapolis or Boise or Folsom or Richardson or San Jose
$206k-$410k/yr OnsiteFull Time
10+ YOE10+ years in digital/ASIC design with chip/design lead ownership; SystemVerilog RTL; synthesis/timing tools; cross-team integration leadership.
SystemVerilog, DC, Genus, PrimeTime, Tempus
2mo
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DMTS Digital Design Engineer / Chip Lead
Minneapolis or Boise or Folsom or Richardson or San Jose
$206k-$410k/yr OnsiteFull Time
10+ YOE10+ years ASIC/digital design experience with prior tape-out; BS/MS/PhD in EE/CE or related; expert SystemVerilog; synthesis (Design Compiler/Genus), static timing analysis (PrimeTime/Tempus), RTL simulation (VCS/Xcelium), CDC tools; chip architecture and IP integration experience.
SystemVerilog, Synopsys Design Compiler, Cadence Genus, PrimeTime, Tempus, VCS, Xcelium, Verdi, DVE, SpyGlass, JasperGold
3mo
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SR RTL DESIGN
Boise, Idaho, United States
HybridFull Time
4+ YOEMaster’s or Bachelor’s in Electrical Engineering with 4+ or 5+ years pre-silicon RTL/ASIC design; Verilog/SystemVerilog; UPF; CDC/RDC; Synthesis and STA; RTL-to-GDS flows.
Verilog, SystemVerilog, UPF, CDC, RDC, Synthesis, STA
1mo
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Principal RTL Design
Boise, Idaho, United States
OnsiteFull Time
8+ YOEMaster's EE with 8+ years or Bachelor's EE with 10+ years RTL/pre-silicon design; ownership of complex RTL/IP, low-power ASIC methodologies (UPF), Verilog/SystemVerilog, STA, synthesis, CDC/RDC experience.
Verilog, SystemVerilog, UPF, CDC, RDC, STA, lint, synthesis
2mo
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SMTS Product Architect
Boise or Folsom or San Jose
$177k-$387k/yr OnsiteFull Time
12+ YOEBachelor's in Electrical Engineering, 12+ years engineering experience, familiarity with LPDDR/DRAM/module architectures, memory hierarchy and SoC/ASIC design, experience with TSV/stacked/3D packaging; mentoring experience preferred.