16 asic engineer jobs at 7 companies in Eliot, ME
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Sr. ASIC Design Engineer, Blink/Ring ASIC Team
North Reading, Massachusetts, United States
$159k-$215k/yr OnsiteFull Time
Bachelor's in Electrical Engineering, knowledge of UVM and Matlab, experience delivering products to volume production, low-power design expertise, RTL coding and debug, and leadership in technical initiatives.
UVM, Matlab, RTL
2mo
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Staff Engineer, Digital ASIC Design (CONTRACT)
Burlington or New York
HybridContract
8+ YOEBS/MS/PhD in EE/CE; 8+ yrs in digital IC/ASIC/SoC; RTL ownership; SystemVerilog/Verilog; high-throughput datapaths; silicon constraints; SV/UVM; Python/cocotb; post-silicon bring-up.
SystemVerilog/Verilog, UVM, Python, cocotb, RTL, RTL verification, Fixed-point modeling
2mo
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ASIC Design Verification Engineer
Irvine or Andover or Broomfield
$129k-$207k/yr OnsiteFull Time
3+ YOEConstrained-random design verification experience using System Verilog/UVM, coverage-driven methodologies, experience with VCS/Incisive and scripting (Python/Perl). Degree with significant related experience required (varies by degree).
System Verilog, UVM, VCS, Incisive, Python, Perl
2w
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ASIC/FPGA Methodology Engineer (TERADYNE, North Reading, MA)
North Reading, Massachusetts, United States
$155k-$248k/yr OnsiteFull Time
3+ YOEBachelor's or master's degree in electrical or computer engineering, 3+ years of FPGA and embedded design experience, and proficiency with design, verification, CI/CD, and Linux tools.
Verilog, Vivado, Quartus, Jenkins, Docker, Git, Linux, LSF, ClearCase, Artifactory, SystemVerilog, UVM
1mo
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ASIC II - AMZ10046576
North Reading, Massachusetts, United States
$136k-$184k/yr OnsiteFull Time
1+ YOEBachelor's in EE/CE or related,1+ year post-silicon validation experience,proficiency in C/C++,C#,Java or Perl,experience designing large-scale embedded software and post-silicon testing.
C++, C#, Java, Perl, SPI, SDIO, MIPI, I2C, UART
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Senior Engineer, Physical Design Engineering (ASIC)
Somerset County or Wilmington
$117k-$161k/yr OnsiteFull Time
5+ YOEExpertise in ASIC/SoC physical design, floorplanning, P&R, timing closure, physical verification, scripting (TCL/Python), and cross-functional collaboration; 5+ years experience preferred.
Cadence, TCL, Python
1w
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Senior Principal FPGA Design Engineer
Manchester or Totowa
OnsiteFull Time
8+ YOERequires 8+ years relevant experience with a bachelor's degree, FPGA or ASIC design, VHDL or Verilog HDL, timing analysis, high-speed interfaces, simulation, scripting, and Secret clearance eligibility.
FPGA, ASIC, VHDL, Verilog HDL, Xilinx Vivado, Intel Quartus, Altera Quartus, Modelsim, Questa, GIT, CVS, Clearcase, Subversion, Perl, Tcl, Python, SERDES, PCIe, DDR2, DDR3, DDR4, LVDS, ADC, DAC
1mo
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Senior Electrical Engineer
Wilmington, Massachusetts, United States
$115k-$173k/yr OnsiteFull Time
5+ YOEBS/MS in Electrical Engineering, 5+ years product development experience, motion control required, embedded microprocessors, PCB layout (Altium) experience, firmware/FPGA/Verilog knowledge, ability to support system-level design and testing.
PCB Layout Tools, Altium, PLD, FPGA, ASIC, Verilog
1mo
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Principal FPGA Digital Design Engineer - Sign-on Bonus
Nashua, New Hampshire, United States
OnsiteFull Time
6+ YOESecret-clearable engineer with 6+ years FPGA/ASIC experience, VHDL/Verilog RTL coding, timing closure, lab debug, familiarity with high-speed interfaces and revision control.
VHDL, Verilog, Xilinx Vivado, Intel/Altera Quartus, ChipScope, SignalTap, ILA, Modelsim, Questa, GIT, CVS, Clearcase, Subversion, Perl, Tcl, Python, shell, Matlab, Simulink, UVM, SystemVerilog, C, C++
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Senior FPGA Design Engineer
Manchester or Nashua
$97k-$165k/yr OnsiteFull Time
4+ YOERequires 4+ years of relevant experience with a bachelor's degree, FPGA or ASIC design experience, VHDL or Verilog HDL, simulation, timing analysis, high-speed interfaces, scripting, and ability to obtain Secret clearance.
VHDL, Verilog HDL, Xilinx Vivado, Intel Quartus, ModelSim, Questa, GIT, CVS, ClearCase, Subversion, Perl, Tcl, Python
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Staff Engineer, Digital Design Engineering
Chelmsford, Massachusetts, United States
$135k-$202k/yr OnsiteFull Time
8+ YOEExpertise in FPGA/ASIC RTL and schematic capture, board-level design, high-speed interfaces, Verilog/VHDL, simulation, and collaboration; U.S. citizenship and ability to obtain Secret clearance required; preferred 8+ years digital design experience.
Verilog, VHDL, 100 GigE, Aurora, PCIe, Allegro, PADS, C#, Python, C/C++, TCL
3mo
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Senior FPGA Design Engineer
Nashua, New Hampshire, United States
$97k-$165k/yr OnsiteFull Time
4+ YOESecret clearance (or eligibility), 4+ years relevant experience with a bachelor’s degree (less with advanced degree). FPGA/ASIC design experience, VHDL/Verilog/SystemVerilog, testbench development, timing closure, revision control, lab testing, and strong communication and debugging skills.
VHDL, Verilog HDL, SystemVerilog, GIT, CVS, Clearcase, Subversion, Matlab/Simulink, Xilinx Vivado, Intel/Altera Quartus, Modelsim/QuestaSim, Perl, Tcl, Python, shell, UVM, C/C++, ILA/chipscope/signaltap, ADC/DAC, SERDES, PCIe
2mo
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
Nashua or Manchester or Largo or New Hampshire or Florida or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree (or equivalent) with 8+ years experience; ability to obtain Secret clearance; expertise in SystemVerilog/UVM, OVM, VHDL, FPGA/ASIC verification and tools; experience with Mentor Questa or Cadence; strong communication and leadership.
SystemVerilog/UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, MATLAB, Simulink
1mo
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
San Diego or Nashua or Austin or Totowa or California or New Hampshire or Texas or New Jersey or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree with 8+ years (or equivalent experience); eligible for Secret clearance; experience with SystemVerilog/UVM/OVM and/or VHDL, Mentor Questa or Cadence tools; FPGA/ASIC verification, test plan development, and strong communication.
SystemVerilog, UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, Matlab, Simulink
2mo
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FAST Labs Hardware Engineering Lead
Merrimack, New Hampshire, United States
$150k-$254k/yr OnsiteFull Time
10+ YOE2+ MgmtBachelor's in engineering, 10+ years progressive hardware experience (8+ in hands-on design), 2+ years leading hardware teams, active DoD Secret clearance (must obtain Top Secret), U.S. person/citizen required, proposal and capture experience.
Model-Based Engineering, Agile, Digital Engineering, RF Systems, GPU, FPGA, ASIC, neuromorphic chips, EO/IR, LiDAR
3mo
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FPGA Design DSP Lead
Nashua or Manchester
$150k-$254k/yr OnsiteFull Time
10+ YOE10+ years experience with bachelor's degree (less with advanced degree); Secret clearance eligible; extensive FPGA/ASIC and DSP experience; VHDL/Verilog coding; Vivado/Quartus, Modelsim/Questa, timing/Cross-domain design, lab debug, mentoring, and high-speed interface knowledge.
VHDL, Verilog HDL, Xilinx Vivado/ISE, Altera Quartus, Modelsim, Questa, PCIe, SerDes, ADC/DAC, DDR3/4, GIT, CVS, Clearcase, Subversion, Tcl/Tk, UNIX/Linux shell, Matlab/Simulink, UVM, System Verilog, C/C++, Perl, Python
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