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ASIC Engineer 2
Longmont, Colorado, United States
$143k-$176k/yr OnsiteFull Time
Define ASIC design/verification requirements; HDL/RTL, scripting; physical design basics; review requirements and collaborate with architects.
Perl, Python, C, Unix shell, Verilog, SystemVerilog, VHDL, RTL
3w
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Principal ASIC Design Engineer
Boulder or Austin
$180k-$220k/yr HybridFull Time
Atom Computing: Building scalable quantum computers using arrays of neutral atoms.
10+ YOEMS/PhD in EE, 10+ years post-degree hardware experience, 2+ full ASIC design cycles, FPGA-to-ASIC experience, SystemVerilog/RTL proficiency, DSP RTL experience, knowledge of Cadence/Synopsys/Siemens EDA, mixed-signal background, mentoring experience.
RTL, SystemVerilog, Cadence, Synopsys, Siemens EDA, FPGA
2mo
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ASIC Engineer 2
Longmont, Colorado, United States
$143k-$176k/yr OnsiteFull Time
Experience with Perl/Python/C/shell scripting, Verilog/System Verilog/VHDL, RTL design and verification, and physical design (layout, timing, power). Master's in ECE or related accepted.
Perl, Python, C, Unix shell, Verilog, System Verilog, VHDL
1mo
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ASIC/FPGA Design Engineer III
Denver or Highlands Ranch or Sunnyvale or Cambridge
$101k-$201k/yr OnsiteFull Time
3+ YOEUS citizen able to obtain DoD Secret clearance, BS in Electrical Engineering (or equivalent), 3+ years professional FPGA development, HDL experience (VHDL/Verilog/SystemVerilog), and experience across ASIC/FPGA lifecycle.
VHDL, Verilog, SystemVerilog, Linux, AMD/Xilinx Vivado, Microchip Libero, Microsoft Project, JIRA, Earned Value Management System (EVMS)
1mo
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Senior Custom ASIC Engineering Lead
San Jose or Fort Collins or Irvine
$144k-$230k/yr OnsiteFull Time
10+ YOEExtensive ASIC physical design and STA experience, multiple tape-outs in advanced nodes, EDA tool and scripting (Tcl, shell) proficiency, knowledge of low-power design, and ability to manage customer ASIC programs. Bachelors+12 yrs or Masters+10 yrs required.
EDA, Tcl, Shell, Verilog
1w
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Verification Engineer
San Jose or San Diego or Austin or Longmont
$124k-$213k/yr HybridFull Time
Experience in IP/ASIC/FPGA verification using UVM, Verilog/SystemVerilog, scripting (Python/Perl), and developing test plans and regression suites; bachelor’s or master’s in computer or electrical engineering.
UVM, Verilog, System Verilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
1w
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Staff FPGA Design Engineer
Berthoud, Colorado, United States
$150k-$180k/yr OnsiteFull Time
10+ YOEB.S. in Electrical Engineering with 10+ years in electronics hardware and ASIC/FPGA development for flight avionics; experience with mixed-signal design, VHDL/Verilog/SystemVerilog, timing closure, EMI/EMC, and hardware verification.
VHDL, Verilog, SystemVerilog, Python, TCL, Xilinx, Microsemi, MATLAB, Simulink, SPICE, Altium, SystemVerilog UVM, C, C++, assembly language, Linux/Windows shell scripting, Cocotb
2mo
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Design Verification (DV) Engineer
Austin or Boulder or Chicago or London or New York City
$175k-$250k/yr OnsiteFull Time
2+ YOE2+ years RTL verification for FPGA/ASIC; SystemVerilog/UVM; Python; Linux; Verilator; Cocotb; C++ is a plus.
SystemVerilog, UVM, Python, Verilator, Cocotb, Linux, C++
3w
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Engineer II - FPGA Verification
Westminster, Colorado, United States
$79k-$135k/yr OnsiteFull Time
2+ YOEBS in Engineering +2 years experience (Master's/PhD may substitute), FPGA/ASIC verification experience, SystemVerilog and UVM proficiency, object-oriented testbench design, coverage-driven verification, and eligibility to obtain Secret clearance; U.S. person required.
System Verilog, UVM, Modelsim, Questa, C++, Windows, Linux, Ruby, Python, TCL
1w
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Principal Electrical Engineer - Denver, CO
Denver, Colorado, United States
$130k-$209k/yr HybridFull Time
12+ YOEB.S. in Electrical Engineering, 12+ years designing complex electrical systems, system architecture experience, technical leadership and mentorship, mixed-signal/analog/digital expertise; medical device or regulated industry experience preferred.
FPGA, ASIC, HDL
3mo
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Senior Principal FPGA Verification Engineer - $30K Sign On Bonus
Westminster, Colorado, United States
$133k-$226k/yr OnsiteFull Time
8+ YOEUS citizen with BS in engineering +8 years experience; strong FPGA/ASIC verification using System Verilog and UVM; testbench, coverage, and verification plan development; familiarity with simulators and scripting languages.
System Verilog, UVM, Modelsim, Questa, C++, Windows, Linux, Ruby, Python, TCL
1w
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SLD Avionics FPGA Engineer III - Lunar Permanence
Seattle or Denver
$120k-$183k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
5+ YOEBachelor's/Master's in engineering or related field,5+ years FPGA/ASIC design and verification,RTL in Verilog/SystemVerilog/VHDL,FPGA tools and simulators,UVM/OVM testbenches,ability to travel ~10%,U.S. work authorization required.
Verilog, SystemVerilog, VHDL, Xilinx Vivado, Intel Quartus, Lattice Diamond, Radiant, Microchip Libero, ModelSim, QuestaSim, Perl, Python, Tcl, Git, SVN, AMBA, AXI, AHB, APB, IEEE 802.3, XAUI, JESD204, I2C, SPI, UVM, OVM
1mo
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SSD Architect
San Jose or Rancho Cordova or Longmont or Vancouver
$196k-$314k/yr HybridFull Time
5+ YOEBachelor's in computer engineering or computer science, 5+ years in embedded systems architecture with ASIC and/or firmware experience; SSD domain expertise, system-level architecture, and cross-functional leadership.
PCIe, NVMe, ASIC
1w
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Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
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