2mo
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ASIC & FPGA Design Engineer Sr.
Orlando, Florida, United States
$101k-$178k/yr HybridFull Time
3+ YOEB.S. in Electrical Engineering or related STEM; 3+ years FPGA design and verification experience; proficiency in VHDL/Verilog/SystemVerilog, Xilinx/AMD toolsets (Vivado, Vitis), Synopsys VCS, UVM, SystemC, Python testbenches; experience with high-speed interfaces and lab debug; U.S. citizen able to obtain Secret clearance.
VHDL, Verilog, SystemVerilog, Vivado, Vitis, Vitis HLS, UltraScale, Synopsys VCS, Synopsys EDA tools, GitLab, UVM, SystemC, Python, Simulink, HDL Coder, C, C++, AXI, Ethernet, TCP/IP, PCIe, Oscilloscope, Spectrum Analyzer, Signal Generator
2mo
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ASIC & FPGA Design Engineer Sr
Orlando, Florida, United States
$101k-$178k/yr HybridFull Time
3+ YOEB.S. in EE or related, 3+ years FPGA design experience, proficiency in VHDL/Verilog/SystemVerilog, Vivado/Vitis toolsets, Synopsys VCS, experience with high-speed interfaces, lab debug skills, US citizenship and ability to obtain DoD Secret clearance.
VHDL, Verilog, SystemVerilog, UVM, SystemC, Python, GitLab, Vivado, Vitis, Vitis HLS, Synopsys VCS, Synopsys Synplify, NCSim, ChipScope, MATLAB/Simulink, HDL Coder, C, C++, tcpdump, Wireshark
1mo
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ASIC & FPGA Design Engineer Stf
Orlando or Florida
$124k-$246k/yr RemoteFull Time
8+ YOEU.S. citizen able to obtain Secret clearance; associate degree or higher in EE/microelectronics; 8+ years full-custom analog/mixed-signal IC layout across 130nm–12nm (including BCD); proficiency with Synopsys Custom Compiler and Cadence Virtuoso; physical verification closure experience.
Synopsys Custom Compiler, Synopsys Custom Designer, Cadence Virtuoso, SKILL, Tcl, Python, Perl, EMIR, DRC, LVS, ERC, ANT
2mo
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Timing Design Engineer
Melbourne, Florida, United States
OnsiteFull Time
2+ YOEBachelors in Electrical Engineering; 2+ years ASIC timing constraints and timing closure; experience with STA tools (Primetime); scripting (Tcl/Perl); strong collaboration skills.
Primetime, SDC constraints, scripting (Tcl, Perl), CAD tools, Synthesis, DFT, backend tools
1mo
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Senior DFT Engineer - LPU
California or North Carolina or Colorado or Arizona or Florida or Massachusetts
$136k-$265k/yr RemoteFull Time
5+ YOE5+ years DFT experience for high-performance ASICs; Bachelor's (or M.S.) in Computer/Electrical Engineering; experience with SCAN/MBIST/ATPG, silicon bring-up and ATE; strong Tcl and Python coding skills.
ATPG, ATPG Streaming SCAN Network (SSN), Tcl, Python, ATE
2w
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Lead Certification AEH Engineer
Minneapolis or Phoenix or Clearwater
$140k-$175k/yr HybridFull Time
5+ YOEBachelor's in Engineering/Aerospace, 5+ years ASIC/FPGA HDL design/verification or AEH certification liaison experience, US person required, familiarity with FAA regulations and certification processes preferred.
2mo
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SLD FPGA Verification Engineer III - Lunar Permanence
Seattle or Space Coast
$131k-$183k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
5+ YOEBS/MS in Electrical or Computer Engineering; 5+ years FPGA/ASIC verification; RTL simulation tools; UVM; testbench development; DO-254 knowledge a plus.
QuestaSim, ModelSim, SystemVerilog, UVM, RTL, DO-254
2mo
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Sr. Specialist, Electrical Engineer - FPGA (37019)
Palm Bay, Florida, United States
OnsiteFull Time
6+ YOEActive experience designing and verifying FPGA/ASIC for wireless communications, DSP, modems, and networking; bachelor's degree or equivalent experience; 6+ years relevant experience; SECRET clearance required.
Vivado, Quartus, MATLAB, Simulink, VHDL
1mo
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Senior Formal Verification Engineer - LPU
California or Texas or Washington or Oregon or Florida
$196k-$311k/yr HybridFull Time
12+ YOE12+ years ASIC verification experience (8+ years in formal); BS/MS/PhD or equivalent; mastery of SystemVerilog Assertions; proficiency with formal tools (JasperGold, VC Formal) and scripting (Tcl, Python); strong communication skills.
SystemVerilog Assertions (SVA), JasperGold, VC Formal, Tcl, Python
3w
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Hardware / Electrical Engineer (FPGA)
Melbourne, Florida, United States
$120k-$140k/yr OnsiteFull Time
Vensure Employer Solutions: Comprehensive HR, payroll, and benefits services for business employers.
8+ YOESTEM degree required; 8+ years experience (8–20 yrs preferred); 5+ years FPGA/ASIC verification; DO-254 (DAL-A) experience required; SystemVerilog/UVM, VHDL/Verilog, Xilinx FPGA preferred; mentoring experience.
SystemVerilog, UVM, VHDL, Verilog, Xilinx FPGA
1mo
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
Nashua or Manchester or Largo or New Hampshire or Florida or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree (or equivalent) with 8+ years experience; ability to obtain Secret clearance; expertise in SystemVerilog/UVM, OVM, VHDL, FPGA/ASIC verification and tools; experience with Mentor Questa or Cadence; strong communication and leadership.
SystemVerilog/UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, MATLAB, Simulink
1mo
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ElectroMechanical Design Engineer Sr Stf: MicroElectronics
Grand Prairie or Orlando
$128k-$256k/yr OnsiteFull Time
U.S. citizen able to obtain Secret clearance. Experience with cable harness concepts, circuit card assembly/printed wiring board design, high-speed PWB constraints, and capturing flowed/derived electromechanical requirements; familiarity with SOC/MCP, ASIC testing, parts/materials selection, flex circuit and microelectronics design; CAMEO familiari...
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