6 asic engineer jobs at 4 companies in Front Royal, VA
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Associate ASIC/FPGA Design or Verification Engineer
El Segundo or Huntington Beach or Fairfax
$99k-$133k/yr OnsiteFull Time
2+ YOEUS citizenship with ability to obtain U.S. Secret clearance, Bachelor\u0000s degree in a relevant field, experience with ASIC/FPGA design or verification, and RTL experience with Verilog/VHDL/SystemVerilog.
Verilog, VHDL, SystemVerilog, System Verilog Assertions, UVM, Palladium, Make, Perl, Python, svn, cvs, git, Linux, ARM, JESD204C, PCIe, Ethernet
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Associate ASIC/FPGA Design or Verification Engineer
El Segundo or Huntington Beach or Fairfax
$99k-$133k/yr OnsiteFull Time
2+ YOEUS citizenship and ability to obtain U.S. Secret clearance; BS in engineering or related field; experience with ASIC/FPGA design or verification and HDL (Verilog/VHDL/System Verilog); familiarity with verification methodologies and scripting.
Verilog, VHDL, System Verilog, System Verilog Assertions, UVM, Palladium, Make, Perl, Python, svn, cvs, git, Linux, JESD204C, PCIe, Ethernet
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Electrical Engineer FPGA/ASIC - Level 3/4 - Dulles
Dulles, Virginia, United States
$114k-$171k/yr OnsiteFull Time
5+ YOEBS with 5+ yrs or MS with 3+ yrs (Level 3) or PhD with 1+ yrs; SCI clearance; VHDL experience; FPGA design flow expertise; aerospace domain knowledge; leadership experience.
VHDL, RTL, Synthesis, Place and Route, Timing Analysis, Power Analysis, Vivado, QuestaSim, MATLAB, Simulink
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Electrical Engineer FPGA/ASIC - Level 3/4 - Dulles
Dulles, Virginia, United States
$114k-$213k/yr OnsiteFull Time
5+ YOERequires active Top-Secret/SCI clearance, VHDL FPGA/ASIC design and verification experience, proficiency in FPGA design flow (synthesis, place and route, static timing), and proven architecture or team leadership; degree with relevant years of experience required.
VHDL, SystemVerilog, MATLAB, Simulink, Vivado, Quartus, QuestaSim, Xilinx, Microchip RTG4, Oscilloscope, Logic analyzer
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FPGA Verification Engineer, Bespoke Solutions
Jessup or Arlington or Herndon
$136k-$184k/yr OnsiteFull Time
4+ YOERequires US citizenship and active TS/SCI clearance; Bachelor's in electrical/communications engineering; 3+ years design and 4+ years verification experience with SystemVerilog/UVM; FPGA/ASIC verification experience.
SystemVerilog, UVM, Xilinx Vivado, AMD Vivado, Synopsys VCS, Cadence Xcelium, SystemVerilog Assertions (SVA)
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Director, Network Development
Nashville or Seattle or United States or Austin or Reston or Santa Clara
$146k-$306k/yr OnsiteFull Time
10+ YOE10+ years experience leading network product engineering, expertise in switching/routing/optical/ASIC platforms, vendor partnerships, hardware qualification, and cross-functional execution.