3mo
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Design Verification Engineer
Austin or Chandler or Greensboro
HybridFull Time
0+ YOEBachelor/Master/PhD in Electrical/Computer Engineering or related field; 2+ years with Bachelors; strong HDL/SystemVerilog/UVM; ASIC/silicon verification experience.
Verilog, VHDL, SystemVerilog, UVM
3mo
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Senior Staff Design Verification Engineer
Austin or Chandler or Greensboro
HybridFull Time
10+ YOEBachelor’s/Master’s/PhD in Electrical or Computer Engineering; 8+ years experience for Masters, 10+ for Bachelor, 6+ for PhD; strong HDL (Verilog/VHDL) and SystemVerilog with UVM; experience verifying silicon/ASICs.
Verilog, VHDL, SystemVerilog, UVM, OVM, AVM, Vera
3mo
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Senior Design Verification Engineer
Austin or Chandler or Greensboro
HybridFull Time
5+ YOEExperience in silicon design/ASIC verification; HDL/SystemVerilog/UVM; cross-disciplinary collaboration.
Verilog, VHDL, SystemVerilog, UVM
3mo
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Staff Design Verification Engineer
Austin or Chandler or Greensboro
HybridFull Time
7+ YOEBachelor's/Master's/PhD in Electrical or Computer Engineering; 7+ (BS), 5+ (MS), 3+ (PhD) years in silicon design/ASIC verification; proficient with Verilog/VHDL and SystemVerilog/UVM; cross-disciplinary collaboration.
Verilog, VHDL, SystemVerilog, UVM, Vera, OVM, HDL
1mo
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DFT Engineer (CE-64000920)
Austin or Chandler or Greensboro
HybridFull Time
2+ YOEMSEE with 2+ years or BS with relevant experience; hands-on ASIC DFT design and verification; experience with FastScan, TestKompress, TetraMAX, Test Compiler; MBIST, scan/ATPG, Verilog/SystemVerilog/VHDL; scripting (Perl, Python, TCL); strong communication.
FastScan, TestKompress, TetraMAX, Test Compiler, Verilog, SystemVerilog, VHDL, Perl, Python, TCL