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ASIC/FPGA Design Engineer IV
Littleton or California or Massachusetts or New York or Colorado or Hawaii or Illinois or Maryland or Minnesota or New Jersey or Vermont or Washington or District of Columbia
$124k-$218k/yr OnsiteFull Time
5+ YOEUS citizen able to obtain and maintain DoD Secret clearance, BS in Computer/Electrical Engineering or equivalent, 5+ years professional experience, HDL experience (VHDL/Verilog/SystemVerilog), ASIC/FPGA design and verification experience, Linux proficiency.
VHDL, Verilog, SystemVerilog, Linux, Microsoft Project, Microsoft Office, Atlassian JIRA, Earned Value Management System (EVMS)
3w
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ASIC Technical Lead- DFT
San Jose or New York City or New York or Washington or Illinois or United States or Canada
$211k-$305k/yr HybridFull Time
10+ YOEBachelor's or Master's in Electrical/Computer Engineering with 10+ years experience; expertise in JTAG, scan and BIST architectures, ATPG and EDA toolsets (TestMax, Tetramax, Tessent, PrimeTime); SystemVerilog/Verilog and post-silicon debug experience.
JTAG, ATPG, TestMax, Tetramax, Tessent, PrimeTime, System Verilog, Verilog
2mo
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Senior FPGA Engineer
Chicago, Illinois, United States
$145k/yr OnsiteFull Time
10+ YOESenior FPGA/ASIC design with Verilog/SystemVerilog; RTL; timing; verification; Python/Bash; strong collaboration; BS in CS/EE; MS a plus.
Verilog, SystemVerilog, VHDL, Python, Bash, RTL
1mo
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FPGA Engineer
Amsterdam or Chicago or London or New York City or Singapore
OnsiteFull Time
Professional FPGA/ASIC design and verification experience; SystemVerilog/Verilog/VHDL and C++; familiarity with EDA tools and scripting (TCL, Python, Bash); university degree in EE/CS/CE or related.
SystemVerilog, Verilog, VHDL, C++, TCL, Python, Bash, EDA
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FPGA Engineer
Chicago, Illinois, United States
$120k-$170k/yr OnsiteFull Time
4+ YOE4+ years FPGA/ASIC experience, expert SystemVerilog and FPGA design, SoC and high-speed transceiver knowledge, simulation/verification skills, degree in EE/CE, strong analytical and collaboration skills.
SystemVerilog
2mo
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Design Verification (DV) Engineer
Austin or Boulder or Chicago or London or New York City
$175k-$250k/yr OnsiteFull Time
2+ YOE2+ years RTL verification for FPGA/ASIC; SystemVerilog/UVM; Python; Linux; Verilator; Cocotb; C++ is a plus.
SystemVerilog, UVM, Python, Verilator, Cocotb, Linux, C++
1mo
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Digital Modem Engineer
Austin or Chicago or New York City or London
$150k-$250k/yr OnsiteFull Time
5+ YOE5+ years in digital modem design, modeling, and implementation; strong FPGA/ASIC knowledge; Python/C/C++/Matlab; MS/PhD in EE/CS or equivalent.
Python, C++, C, Matlab
2mo
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Physical Design Engineer
Austin or Boulder or Chicago or London or New York City or Seattle
$200k-$300k/yr OnsiteFull Time
Experience in high-performance ASIC design; digital logic; DFT concepts; scripting (Python, Tcl, shell); static timing analysis; timing closure; Innovus/PrimeTime.
Innovus, PrimeTime, Python, Tcl, shell
1mo
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Principal/ Sr. Principal FPGA Design Engineer
Rolling Meadows, Illinois, United States
$120k-$224k/yr OnsiteFull Time
5+ YOEUS citizen able to obtain Top Secret/SCI; Bachelor's in EE/CE (or similar); 5+ years FPGA/ASIC design (8+ for senior); VHDL/Verilog, HLS (Xilinx Vivado HLS/Mentor Catapult), Python/C/C++, DSP and FPGA toolchain experience.
VHDL, Verilog, Xilinx Vivado HLS, Mentor Catapult HLS, C++, Python, C, Electronic Design Automation (EDA) Tools, Mentor Graphics ModelSim, QuestaSim, Synplify, Xilinx ISE, Vivado, Intel Quartus, Altera SOPC Builder, Altera Qsys, DSP Builder, SystemVerilog, Universal Verification Methodology (UVM), MATLAB, Simulink, AXI, PCIe, Xilinx Aurora, JESD, 10G Ethernet, GIT, SVN, ClearCase, DOORS, Jira, Rally, ClearQuest, Signal Generators, Logic Analyzers, Digital Oscilloscopes
1mo
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Principal/ Sr. Principal FPGA Design Engineer
Rolling Meadows, Illinois, United States
$120k-$224k/yr OnsiteFull Time
5+ YOEUS citizen able to obtain Top Secret/SCI clearance; B.S. in EE/CE or similar plus 5+ years FPGA/ASIC design (8+ for senior level). Requires VHDL/Verilog, HLS (Vivado/Mentor Catapult), timing closure, DSP knowledge, Python/C/C++, testbench and FPGA design flow experience.
VHDL, Verilog, Xilinx Vivado HLS, Mentor Catapult HLS, C++, Python, C, MATLAB, Simulink, Mentor Graphics ModelSim, QuestaSim, Synplify, Xilinx ISE, Xilinx Vivado, Intel Quartus, Altera SOPC Builder, Altera Qsys, DSP Builder, SystemVerilog, Universal Verification Methodology (UVM), GIT, SVN, ClearCase, DOORS, Jira, Rally, ClearQuest, AXI, PCIe, Xilinx Aurora, JESD, 10G Ethernet
1mo
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Design Verification Engineering Lead - Silicon One
San Jose or New York City or New York or Washington or Illinois or United States or Canada
$211k-$305k/yr OnsiteFull Time
5+ YOEDegree plus extensive ASIC DV experience (Bachelors+12/Masters+8/PhD+5), recent Verilog/SystemVerilog/UVM experience, scripting (Perl or Python), ASIC verification, emulation and bring-up experience.
Verilog, SystemVerilog, UVM, Perl, Python, Linux, C, C++, Veloce, Palladium, Zebu, HAPS, Jasper Gold, Cursor, Codex, CoPilot, P4
1mo
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Research Engineer, Pre-Training
Chicago or London or New York City
$300k-$350k/yr OnsiteFull Time
Expert in large-scale distributed training, HPC or distributed systems, GPUs/TPUs and high-performance networking, Python and PyTorch/JAX; published research and advanced degree (MS/PhD) or equivalent industry experience.
GPUs, TPUs, NVLink, InfiniBand, Kubernetes, Slurm, Python, PyTorch, JAX, CUDA, Triton, Pallas, CuTe, XLA, FPGA, ASIC
2w
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MBIST Technical Leader
San Jose or Austin or New York City or New York or Washington or Illinois or United States or Canada
$211k-$305k/yr HybridFull Time
10+ YOEBachelor's in Electrical Engineering with 12+ years (or Master's with 10+ years) ASIC DFT experience; memory architecture and failure-mode experience; industry DFT tools; scripting (Python, Tcl, Perl); strong communication and test strategy skills.
Synopsys DesignWare, SMS, TestMax, Mentor Graphics Tessent, Python, Tcl, Perl, Verilog, SystemVerilog