18 asic engineer jobs at 5 companies in Liberty, NC
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Senior ASIC Design Engineer - Agentic AI
Santa Clara or Austin or Durham
$168k-$311k/yr OnsiteFull Time
8+ YOEMaster's/PhD or equivalent experience, 8+ years experience, micro-architecture and RTL (Verilog) expertise, ASIC design flow knowledge, Python prototyping, experience with LLM fine-tuning, RAG pipelines, and vector databases.
Verilog, Python, RAG pipelines, vector databases, large language models
2mo
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Senior ASIC Front End Infrastructure Engineer
Santa Clara or Westford or Austin or Durham
$184k-$357k/yr OnsiteFull Time
8+ YOE8+ years experience; Masters in Electrical Engineering, Computer Engineering, Computer Science or related; Python/Perl; AI tooling; Make; CI (Jenkins); strong problem solving; ASIC/CPU verification knowledge.
Python, Perl, Make, Jenkins
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Senior ASIC Power Engineer
Santa Clara or Austin or Durham or United States
$136k-$265k/yr OnsiteFull Time
5+ YOEBS or MS in electrical engineering or computer science; 5+ years in high-performance processor designs; SystemVerilog or HDL; VLSI/physical design; strong communication; computer architecture.
SystemVerilog, HDL, VLSI, RTL
2w
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Senior ASIC Verification Engineer
Durham, North Carolina, United States
$136k-$265k/yr HybridFull Time
5+ YOE5+ years verification experience, degree in EE/CS/CE or equivalent, strong verification methodology and debugging skills, fluency in C++/SystemVerilog, experience with VCS, Debussy, GDB, and UVM.
C++, SystemVerilog, VCS, Debussy, GDB, UVM
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Senior ASIC Design Engineer - GPU
Durham or Madison or Hillsboro
$136k-$265k/yr HybridFull Time
5+ YOE5+ years relevant experience; BS/MS in EE/CS/CE or equivalent; proficiency in Verilog, SystemVerilog, C++; experience with memory subsystems; strong communication and mentoring skills.
Verilog, SystemVerilog, VCS, Verdi, Synopsys, C++
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ASIC Design Efficiency Engineer
Santa Clara or Austin or Durham
$116k-$219k/yr OnsiteFull Time
2+ YOEBachelors in EE/CE,2+ years experience,proficiency in SystemVerilog,strong logic design and computer architecture knowledge,EM skills and teamwork; Python/Perl scripting a plus.
SystemVerilog, Python, Perl
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Senior ASIC Design Verification Infrastructure and Tools Engineer – GPU
Santa Clara or Westford or Austin or Durham or California
$136k-$265k/yr OnsiteFull Time
5+ YOEBS/MS or equivalent experience; 5+ years relevant experience; ASIC workflows, UVM, Verilog/SystemVerilog, simulation/debug tools, Python or Perl, and root-cause analysis skills required.
UVM, Verilog, SystemVerilog, VCS, Verdi, Xcelium, Python, Perl
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Senior Principal Engineer, Architecture ASIC / System
Toronto or Ottawa or Burlington or Irvine or Morrisville or Santa Clara or Westborough
$192k-$255k/yr OnsiteFull Time
14+ YOESenior architect with 14+ years in system architecture for SoC; expertise in interconnects, memory hierarchies, power management, security; strong technical leadership.
IP evaluation, IP block, SoC architecture
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Senior ASIC Physical Design Engineering Technical Lead
San Jose or Austin or Research Triangle Park
$211k-$305k/yr HybridFull Time
5+ YOEAdvanced degree in Electrical Engineering with significant physical design experience (BSc+12y / MSc+8y / PhD+5y), RTL-to-GDSII/tapeout experience at 7nm/5nm/3nm, EDA tool proficiency, UPF low-power methods, Python and AI tools experience.
Innovus, Tempus/Primetime, Redhawk/Voltus, Calibre/Pegasus, UPF, Python, RTL2GDSII, Flex-HTree, AI tools
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ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead (Remote)
San Jose or Research Triangle Park or Acton or Dallas or Tempe or Cary or Carlsbad or Colorado Springs
$184k-$264k/yr RemoteFull Time
3+ YOEBachelor's/MS/PhD in Electrical Engineering with 3+ to 8+ years SI/PI experience; expertise in high-speed design, SI/PI simulation, layout review, SPICE; mentoring and leadership experience.
Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, Ansys EM, SPICE, Vector Network Analysis, IBIS
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Staff Engineer - Digital ASIC and Signal Processing Chip Architect/Systems Engineer
Durham, North Carolina, United States
$131k-$190k/yr OnsiteFull Time
10+ YOE10+ years of experience, including 5 years in digital IC design; expertise in digital signal processing, RTL design, digital architecture; firmware and embedded software; radio architecture; microprocessor subsystems; experience across hardware-software co-design.
SystemVerilog, MATLAB, Python, DSP cores
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Senior Principal Engineer, Design Verification
Morrisville, North Carolina, United States
$184k-$273k/yr OnsiteFull Time
12+ YOEDegree in CS/EE or related plus 12+ to 20+ years of ASIC verification experience; strong ASIC verification methodology, SoC/emulation/lab bring-up experience, leadership and communication skills.
2mo
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DFT Engineer (CE-64000920)
Austin or Chandler or Greensboro
HybridFull Time
2+ YOEMSEE with 2+ years or BS with relevant experience; hands-on ASIC DFT design and verification; experience with FastScan, TestKompress, TetraMAX, Test Compiler; MBIST, scan/ATPG, Verilog/SystemVerilog/VHDL; scripting (Perl, Python, TCL); strong communication.
FastScan, TestKompress, TetraMAX, Test Compiler, Verilog, SystemVerilog, VHDL, Perl, Python, TCL
2mo
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Staff Engineer, Design Verification
Morrisville, North Carolina, United States
$115k-$170k/yr OnsiteFull Time
12+ YOEExtensive ASIC verification experience leading DV architecture, emulation, post-silicon validation and delivery; strong leadership, communication, and cross-functional skills. Advanced degree plus many years of related experience required.
3w
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Principal Technical Engineer 3rd Party IP Engineer
Morrisville or Austin or New York or Burlington or Westborough or Boise
$152k-$225k/yr OnsiteFull Time
3+ YOEBachelor’s in CS/EE with 5-10 years or Master/PhD with 3-5 years; deep DDR/LPDDR/GDDR/HBM/eMMC interface knowledge, ASIC design flow experience, 3rd-party IP management, project and customer communication skills.
DDR, LPDDR, GDDR, HBM, eMMC, logic synthesis, physical design, timing, DRC/LVS, Formal verification, Design-For-Test, DFT
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Senior Network Solution Engineer (Weekend Coverage)
Santa Clara or Westford or Austin or Durham or Redmond or New York
$140k-$270k/yr OnsiteFull Time
5+ YOE5+ years software development (C, C++, Python, or Go) in the networking industry, 5+ years supporting in-field production network equipment, bachelor's degree or equivalent, experience with Linux NIC drivers/ASICs/firmware/network OS, expert Ethernet/IP knowledge.
C, C++, Python, Go, Linux, InfiniBand, NVLink, Spectrum-X
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Senior Security Architect - Hardware
Santa Clara or Austin or Hillsboro or Durham or Redmond
$184k-$357k/yr OnsiteFull Time
8+ YOE8+ years relevant experience; BS/MS/PhD (or equivalent) in EE/CS/CE; experience with SoC/GPU ASIC design, HW root of trust, secure boot; programming in C/C++, Verilog, ARM assembly, Python/Perl; strong communication skills.
C/C++, Verilog, ARM assembly, Python, Perl, TPM
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Customer Delivery Architect (Remote)
Research Triangle Park or San Jose or Seattle
$167k-$234k/yr RemoteFull Time
10+ YOEBachelor’s in CS/EE or equivalent, 10+ years in networking/hyperscale infrastructure, deep SONiC and data center networking expertise, strong troubleshooting, Linux and automation skills.
SONiC, Linux, Python, Git, Docker, Kubernetes, Switch Abstraction Interface (SAI), Redis, CI/CD, RoCE (RDMA over Converged Ethernet), Silicon One, Silicon One SDK, NCS5500, Catalyst 8000, Nexus 3000, Nexus 9000, NCS1K, ASIC
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