42 asic engineer jobs at 15 companies in Louisville, CO
9h
Save
Mark Applied
Hide
Senior ASIC Verification Engineer (PCIe/CXL)
San Jose or San Diego or Austin or Longmont
$146k-$250k/yr HybridFull Time
Expertise in ASIC verification, Verilog, SystemVerilog, UVM testbenches, and Python or Perl scripting; experience with PCIe, CXL, NVMe, or Ethernet; bachelor's or master's degree in computer or electrical engineering.
FPGA, ASIC, UVM, Verilog, SystemVerilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
6d
Save
Mark Applied
Hide
Senior ASIC Design Engineer
Boulder or Austin
$140k-$175k/yr HybridFull Time
Atom Computing: Building scalable quantum computers using arrays of neutral atoms.
5+ YOERequires a master's or PhD in electrical engineering or related field, 5+ years of hardware engineering experience, a complete ASIC cycle, DSP, RTL/SystemVerilog, FPGA, and EDA tool expertise.
SystemVerilog, RTL, FPGA, Cadence, Synopsys, Siemens EDA
4d
Save
Mark Applied
Hide
ASIC & FPGA Design Engineer Stf - E4
Littleton or Sunnyvale or Denver or Boulder or Louisville or Highlands Ranch or King of Prussia
$136k-$252k/yr OnsiteFull Time
Bachelor of Science in Electrical Engineering or related field, or equivalent experience; ASIC/FPGA design, debugging, or verification experience; active Top Secret clearance and U.S. citizenship required.
ASIC, FPGA, Microsoft Project, Microsoft Office, Atlassian JIRA, Earned Value Management System (EVMS)
2w
Save
Mark Applied
Hide
Analog ASIC Design Engineer
Boulder or Louisville or Beaverton
HybridFull Time
5+ YOEBSEE or MSEE in EE, 5+ years analog/mixed‑signal IC design experience, ASIC design and verification tool proficiency, RF and layout experience, lab characterization, strong communication and collaboration skills.
Ansys HFSS, Cadence EMX
2w
Save
Mark Applied
Hide
Analog ASIC Design Engineer
Boulder or Beaverton
$149k-$277k/yr OnsiteFull Time
5+ YOEBSEE/MSEE and 5+ years analog/mixed-signal IC design experience, proficiency with ASIC design tools, layout and RF analysis, strong communication, willingness to travel domestically, must be a U.S. Person.
Ansys HFSS, Cadence EMX
2mo
Save
Mark Applied
Hide
Senior Custom ASIC Engineering Lead
San Jose or Fort Collins or Irvine
$144k-$230k/yr OnsiteFull Time
10+ YOEExtensive ASIC physical design and STA experience, multiple tape-outs in advanced nodes, EDA tool and scripting (Tcl, shell) proficiency, knowledge of low-power design, and ability to manage customer ASIC programs. Bachelors+12 yrs or Masters+10 yrs required.
EDA, Tcl, Shell, Verilog
4d
Save
Mark Applied
Hide
Senior Digital Signal Processing (DSP) Engineer
Englewood, Colorado, United States
$130k-$185k/yr OnsiteFull Time
10+ YOEBSEE and 10+ years of experience required. Requires DSP, RF communications, MATLAB, C/C++, Verilog or VHDL, FPGA or ASIC implementation, communication skills, and US citizenship.
MATLAB, C, C++, Verilog, VHDL, FPGA, ASIC
2w
Save
Mark Applied
Hide
Hardware Engineer
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$91k-$113k/yr OnsiteFull Time
Early-career candidates pursuing or recently completing an engineering degree; familiarity with hardware, firmware, ASIC/SoC, or systems; programming and design experience through coursework or projects; strong analytical and communication skills.
Verilog/SystemVerilog, RTL, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, Git, Linux, IDE, CAD, Microsoft Office, RTOS
4d
Save
Mark Applied
Hide
Senior FPGA Development Engineer
Boulder, Colorado, United States
$146k-$190k/yr OnsiteFull Time
Bachelor's degree in electrical or computer engineering; progressively responsible FPGA, ASIC, or digital-logic experience; expert VHDL, Verilog, or SystemVerilog; verification, implementation, and technical leadership expertise.
VHDL, Verilog, SystemVerilog, Git, Jira, Confluence, DOORS, Microsoft?, AMD Versal, UltraScale+, Zynq, Microchip PolarFire, PolarFire SoC, Lattice Nexus, SpaceWire, SpaceFibre, AXI, Ethernet, SPI, PCIe, JESD204, LVDS, DDR3, DDR4, ONFI NAND, eMMC, MRAM, UVM, cocotb, Python, Tcl
3mo
Save
Mark Applied
Hide
Principal Engineer, Firmware
Longmont, Colorado, United States
$161k-$275k/yr OnsiteFull Time
7+ YOELead firmware architecture for SSDs; 7+ years embedded firmware; C/C++, Python; ASIC/FPGA bring-up; strong communication.
C, C++, Python
1mo
Save
Mark Applied
Hide
Staff FPGA Design Engineer
Berthoud, Colorado, United States
$150k-$180k/yr OnsiteFull Time
10+ YOEB.S. in Electrical Engineering with 10+ years in electronics hardware and ASIC/FPGA development for flight avionics; experience with mixed-signal design, VHDL/Verilog/SystemVerilog, timing closure, EMI/EMC, and hardware verification.
VHDL, Verilog, SystemVerilog, Python, TCL, Xilinx, Microsemi, MATLAB, Simulink, SPICE, Altium, SystemVerilog UVM, C, C++, assembly language, Linux/Windows shell scripting, Cocotb
1mo
Save
Mark Applied
Hide
Space Electrical Chief Engineer
Englewood, Colorado, United States
$141k-$252k/yr OnsiteFull Time
13+ YOEExtensive spacecraft electrical experience (system architecture, power, avionics, EEE parts), ability to obtain DoD clearance, 13+ years engineering experience (or equivalent), leadership of multidisciplinary teams, requirements and test oversight.
DOORS, SpaceWire, CAN, MIL STD 1553, Ethernet, FPGA, ASIC, HIL, EMC, EMI, MBSE, MIL STD 1540, MIL STD 461, NASA GEVS
1mo
Save
Mark Applied
Hide
Engineer II - FPGA Verification
Westminster, Colorado, United States
$79k-$135k/yr OnsiteFull Time
2+ YOEBS in Engineering +2 years experience (Master's/PhD may substitute), FPGA/ASIC verification experience, SystemVerilog and UVM proficiency, object-oriented testbench design, coverage-driven verification, and eligibility to obtain Secret clearance; U.S. person required.
System Verilog, UVM, Modelsim, Questa, C++, Windows, Linux, Ruby, Python, TCL
1mo
Save
Mark Applied
Hide
Principal Electrical Engineer - Denver, CO
Denver, Colorado, United States
$130k-$209k/yr HybridFull Time
12+ YOEB.S. in Electrical Engineering, 12+ years designing complex electrical systems, system architecture experience, technical leadership and mentorship, mixed-signal/analog/digital expertise; medical device or regulated industry experience preferred.
FPGA, ASIC, HDL
1mo
Save
Mark Applied
Hide
SLD Avionics FPGA Engineer III - Lunar Permanence
Seattle or Denver
$120k-$183k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
5+ YOEBachelor's/Master's in engineering or related field,5+ years FPGA/ASIC design and verification,RTL in Verilog/SystemVerilog/VHDL,FPGA tools and simulators,UVM/OVM testbenches,ability to travel ~10%,U.S. work authorization required.
Verilog, SystemVerilog, VHDL, Xilinx Vivado, Intel Quartus, Lattice Diamond, Radiant, Microchip Libero, ModelSim, QuestaSim, Perl, Python, Tcl, Git, SVN, AMBA, AXI, AHB, APB, IEEE 802.3, XAUI, JESD204, I2C, SPI, UVM, OVM
2w
Save
Mark Applied
Hide
Pre-Silicon Diagnostics Engineer
Arizona or Bloomington or Fort Collins
$106k-$243k/yr RemoteFull Time
4+ YOE4+ years experience in diagnostics/validation/firmware/embedded software for ASICs; proficiency in object-oriented programming, Python, Linux; strong debugging, networking fundamentals, and communication skills.
Python, Linux, UVM, Verilog, SystemVerilog
2w
Save
Mark Applied
Hide
Pre-Silicon Diagnostics Engineer
Arizona or Bloomington or Fort Collins
$106k-$243k/yr RemoteFull Time
4+ YOEDevelop diagnostics and emulator-based validation for ASICs, proficient in Python,OOP,Linux,knowledge of high-speed networking;4+ years experience;strong written and verbal English.
Python, Linux, UVM, Verilog, SystemVerilog
2w
Save
Mark Applied
Hide
Pre-Silicon Diagnostics Engineer
Arizona or Bloomington or Fort Collins
$106k-$243k/yr RemoteFull Time
4+ YOEExperience in diagnostics/validation/firmware/embedded software for ASICs, 4+ years experience, proficiency in object-oriented programming, Python, Linux, networking fundamentals, strong debug and communication skills.
Python, Linux, UVM, Verilog, SystemVerilog
2mo
Save
Mark Applied
Hide
Senior FPGA Verification Engineer - $30K Sign On Bonus
Westminster, Colorado, United States
$97k-$165k/yr HybridFull Time
4+ YOEBS in engineering plus 4+ years related experience (or equivalent), strong FPGA/ASIC verification skills with System Verilog and UVM, coverage-driven verification, class-based constrained-random testbenches, and strong communication skills; eligible for U.S. security clearance.
System Verilog, UVM, Modelsim, Questa, C++, Windows, Linux, Ruby, Python, TCL
2mo
Save
Mark Applied
Hide
SSD Architect
San Jose or Rancho Cordova or Longmont or Vancouver
$196k-$314k/yr HybridFull Time
5+ YOEBachelor's in computer engineering or computer science, 5+ years in embedded systems architecture with ASIC and/or firmware experience; SSD domain expertise, system-level architecture, and cross-functional leadership.
PCIe, NVMe, ASIC
Explore Jobs