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1 asic engineer job at 1 company in Niles, OH

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Senior Design Verification Engineer
Tempe or Independence
$156k-$291k/yr RemoteFull Time
Viasat
ViasatNASDAQ: VSAT: Provides global satellite broadband and secure networking communication services.
8+ YOE8+ years design verification experience with UVM, SystemVerilog, RTL verification for FPGA/ASIC, Bachelor's in EE/CE, US citizenship, ability to obtain Secret clearance, familiarity with Questa/Xcelium/VCS and AI verification tools.
Universal Verification Methodology (UVM), SystemVerilog, VHDL, Verilog, Questa, Xcelium, VCS, Jira
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