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Mark Applied
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Principal Engineer - FPGA/ASIC Design
Indianapolis or West Lafayette
$113k-$184k/yr HybridFull Time
3+ YOEU.S. citizen with degree in electronics/computer engineering and 3+ years experience (or higher degree), expertise in FPGA/ASIC design (VHDL/Verilog/SystemVerilog), DO-254 verification, timing closure, synthesis, testbenches, lab validation, and scripting (TCL/Python/Shell).
VHDL, Verilog, SystemVerilog, DO-254, TCL, Python, Shell, Windows, Linux, Git, SVN, Actel, Xilinx, MATLAB, Simulink, Cameo Systems Modeler (MagicDraw), ILA, JTAG, oscilloscopes, logic analyzers