4d
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Lead ASIC Digital Design Engineer
Annapolis Junction or Telework or Boise or Salt Lake City or Bloomington
$177k-$187k/yr RemoteFull Time
8+ YOE8+ years ASIC/FPGA RTL design experience, ASIC tape-out and timing-closure experience, familiarity with FinFET nodes and commercial foundry flows, EDA tool and JIRA proficiency, strong RTL and microarchitecture skills.
JIRA, Microsoft Office
5d
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Senior ASIC Digital Design Engineer
Annapolis Junction or Boise or Salt Lake City or Bloomington or United States
$142k-$150k/yr RemoteFull Time
5+ YOEBachelor's in ECE or related and 5+ years experience (or Master's+3); US citizenship and ability to obtain DoD Secret clearance; strong RTL/ASIC design and verification experience.
JIRA, Microsoft Office
2w
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ASIC FPGA Engineer (New Hire Sign On Bonus Eligible)
Bloomington, Minnesota, United States
$114k-$121k/yr OnsiteFull Time
2+ YOEBachelor in Electrical/Computer Engineering (or related) plus 2 years experience (or Master plus 6 months); ability to obtain DoD Secret clearance; U.S. citizenship required; SystemVerilog preferred; Microsoft Office and ASIC/FPGA tool experience.
Microsoft Office, System Verilog, FPGA
1w
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ASIC Design Verification Engineer
Minneapolis, Minnesota, United States
OnsiteFull Time
2+ YOE2+ years IP/SoC verification experience with UVM, SystemVerilog, and Python; bachelor’s or master’s in EE/CE; strong debugging, analytical, and communication skills.
UVM, SystemVerilog, Python
2mo
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Principal Engineer, ASIC Physical Design
Minneapolis, Minnesota, United States
OnsiteFull Time
15+ YOE15+ years hands-on ASIC physical design; BA/MA in EE/ Electronics/ Computer Architecture; multiple production tape-outs; strong low-power techniques; scripting (Tcl/Perl/Python).
Synopsys, Cadence, Calibre, UPF/CPF, Tcl, Perl, Python
2mo
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Engineer, ASIC Physical Design
Minneapolis, Minnesota, United States
$143k-$176k/yr HybridFull Time
Master's degree in Electrical or Computer Engineering; floorplanning/placement/routing; timing analysis; Cadence/Synopsys tools; Mentor IC Validator; Tcl/Cshell; design and verification collaboration.
Cadence Innovus, Cadence Tempus, Synopsys ICC2, Synopsys Fusion Compiler, Synopsys Primetime, Mentor Calibre, IC Validator, Hercules, Tcl, Cshell
3w
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FPGA Engineer (New Hire Bonus Eligible)
Bloomington, Minnesota, United States
$117k-$1127k/yr OnsiteFull Time
2+ YOEBachelor's in Electrical/Computer Engineering required (or Master's with reduced experience), 2+ years relevant experience, US citizenship, ability to obtain DoD Secret clearance, ASIC/FPGA design and verification experience, Microchip PolarFire, UVM, SystemVerilog, Microsoft Office.
Microchip Polarfire, UVM, SystemVerilog, Microsoft Office
2mo
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Sr Engineer – Network Operating Systems
Brooklyn Park, Minnesota, United States
$98k-$176k/yr HybridFull Time
5+ YOE4-year degree or equivalent; 5+ years software development; strong C/C++; Linux; Python; Docker; networking; I2C; hardware/embedded; Agile/Scrum.
C, C++, Python, Shell, Git, Make, Docker, Linux, Systemd, Build Tools, Packages, TLS, DNS, BGP, LACP, LLDP, VLANs, I2C, Networking, ASIC, Memory-mapped I/O