Saint Louis Park • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Saint Louis Park • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Saint Louis Park • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Saint Louis Park • 50 milesRemote · Hybrid · Onsite · Field · All Environments
11 asic engineer jobs at 4 companies in Saint Louis Park, MN
3w
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Lead ASIC Digital Design Engineer
Annapolis Junction or Boise or Salt Lake City or Bloomington or United States
$177k-$187k/yr RemoteFull Time
8+ YOEBachelor's in ECE or related plus 8+ years (or Master's plus 6+ years), strong RTL/ASIC/FPGA design experience, ASIC tape-out and timing closure experience, ability to obtain DoD Secret clearance, proficiency with JIRA and Microsoft Office.
JIRA, Microsoft Office
3w
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Senior ASIC Digital Design Engineer
Annapolis Junction or Boise or Salt Lake City or Bloomington or United States
$142k-$150k/yr RemoteFull Time
5+ YOEBachelor's in Electrical/Computer Engineering (or related) with 5+ years experience (Master's+3 acceptable), U.S. citizenship, ability to obtain DoD Secret clearance, 5–8+ years ASIC/FPGA RTL design experience, formal verification and verification-process experience, JIRA and Microsoft Office proficiency.
JIRA, Microsoft Office, STA
3mo
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Principal Engineer, ASIC Physical Design
Minneapolis, Minnesota, United States
OnsiteFull Time
15+ YOE15+ years ASIC physical design experience, bachelor's or master's in EE/electronics/computer architecture, production tape-outs, UPF/CPF low-power expertise, scripting in Tcl/Perl/Python, Synopsys/Cadence/Calibre experience.
Synopsys, Cadence, Calibre, Tcl, Perl, Python, UPF, CPF
1mo
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ASIC Design Verification Engineer
Minneapolis, Minnesota, United States
OnsiteFull Time
2+ YOEBachelor's or Master's in EE/CE,2+ years IP/SoC verification experience, UVM constrained-random experience, strong SystemVerilog and Python skills, analytical debugging and communication skills.
UVM, SystemVerilog, Python
1mo
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ASIC Design Verification Engineer
Minneapolis, Minnesota, United States
OnsiteFull Time
2+ YOE2+ years IP/SoC verification experience with UVM, SystemVerilog, and Python; bachelor’s or master’s in EE/CE; strong debugging, analytical, and communication skills.
UVM, SystemVerilog, Python
3mo
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Principal Engineer, ASIC Physical Design
Minneapolis, Minnesota, United States
OnsiteFull Time
15+ YOE15+ years hands-on ASIC physical design; BA/MA in EE/ Electronics/ Computer Architecture; multiple production tape-outs; strong low-power techniques; scripting (Tcl/Perl/Python).
Synopsys, Cadence, Calibre, UPF/CPF, Tcl, Perl, Python
1d
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Principal Digital Design Engineer / Chip Lead
Minneapolis or Richardson or Boise
OnsiteFull Time
10+ YOEBS, MS, or PhD in engineering; 10+ years of ASIC/digital design experience with prior tape-out; expert SystemVerilog; synthesis, timing analysis, RTL simulation, CDC, IP integration, and technical leadership experience.
SystemVerilog, Synopsys Design Compiler, Cadence Genus, PrimeTime, Tempus, VCS, Xcelium, Verdi, DVE, SpyGlass, JasperGold CDC, I2C, PRBS
2w
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Pre-Silicon Diagnostics Engineer
Arizona or Bloomington or Fort Collins
$106k-$243k/yr RemoteFull Time
4+ YOE4+ years experience in diagnostics/validation/firmware/embedded software for ASICs; proficiency in object-oriented programming, Python, Linux; strong debugging, networking fundamentals, and communication skills.
Python, Linux, UVM, Verilog, SystemVerilog
2w
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Pre-Silicon Diagnostics Engineer
Arizona or Bloomington or Fort Collins
$106k-$243k/yr RemoteFull Time
4+ YOEDevelop diagnostics and emulator-based validation for ASICs, proficient in Python,OOP,Linux,knowledge of high-speed networking;4+ years experience;strong written and verbal English.
Python, Linux, UVM, Verilog, SystemVerilog
2w
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Pre-Silicon Diagnostics Engineer
Arizona or Bloomington or Fort Collins
$106k-$243k/yr RemoteFull Time
4+ YOEExperience in diagnostics/validation/firmware/embedded software for ASICs, 4+ years experience, proficiency in object-oriented programming, Python, Linux, networking fundamentals, strong debug and communication skills.
Python, Linux, UVM, Verilog, SystemVerilog
2w
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Thermal Imaging Platform Architect
Bloomington or Florida or Texas
$159k-$238k/yr OnsiteFull Time
8+ YOEBS in engineering, physics, or materials science; 8–12+ years in semiconductor applications, design, or process development; analog, mixed-signal, ASIC, CMOS, Cadence, customer engagement, and 25% travel experience.
Cadence, PDK, DRC