42 asic engineer jobs at 14 companies in Sandy, OR
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Senior ASIC Design Engineer
Vancouver, Washington, United States
$116k-$182k/yr OnsiteFull Time
8+ YOEBS/MS in electrical engineering with 8+ years ASIC/SoC design experience; RTL-to-silicon expertise, Synopsys/Cadence tool experience, Verilog/SV and scripting languages, strong communication and problem-solving skills.
Synopsys, Cadence, Verilog, SV, Python, Perl, C, C++, subversion, git, GitHub, AI Copilot
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Senior ASIC Design Engineer
Vancouver, Washington, United States
$116k-$182k/yr OnsiteFull Time
8+ YOEBS/MS in electrical engineering,8+ years ASIC/SoC design experience,RTL-to-silicon expertise,experience with Synopsys and Cadence tools,proficiency in Verilog,SV,Python,Perl,C/C++,and code management (git,subversion).
Synopsys, Cadence, Verilog, SV, Python, Perl, C, C++, subversion, git, GitHub, AI Copilot
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Senior ASIC Design Engineer
Vancouver, Washington, United States
$116k-$182k/yr OnsiteFull Time
8+ YOEBS/MS in electrical engineering with VLSI focus,8+ years ASIC/SoC design experience,RTL-to-silicon expertise,knowledge of Synopsys and Cadence flows,proficiency in Verilog/SV,Python,Perl,C/C++,and code management (git,subversion).
Synopsys, Cadence, Verilog, SV, Python, Perl, C, C++, Subversion, git, GitHub, FPGA, AI Copilot (LLM-based tools)
2mo
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Senior ASIC Verification Engineer
Durham or Madison or Hillsboro
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelor's or Master's in EE/CS/CE (or equivalent), 5+ years ASIC verification experience, strong SystemVerilog and C/C++ skills, UVM, constrained-random and coverage-driven verification, familiarity with VCS/IES and debug tools.
SystemVerilog, C, C++, Universal Verification Methodology (UVM), VCS, IES, Debussy, GDB, Semiformal Verification (SFV), Perl, Python
22h
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ASIC Design and Integration Engineer
Beaverton, Oregon, United States
OnsiteFull Time
Highly skilled ASIC design engineer developing custom SoCs and collaborating with cross-functional teams to deliver advanced technology solutions.
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Analog ASIC Design Engineer
Boulder or Beaverton
$149k-$277k/yr OnsiteFull Time
5+ YOEBSEE/MSEE and 5+ years analog/mixed-signal IC design experience, proficiency with ASIC design tools, layout and RF analysis, strong communication, willingness to travel domestically, must be a U.S. Person.
Ansys HFSS, Cadence EMX
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Analog ASIC Design Engineer
Boulder or Louisville or Beaverton
HybridFull Time
5+ YOEBSEE or MSEE in EE, 5+ years analog/mixed‑signal IC design experience, ASIC design and verification tool proficiency, RF and layout experience, lab characterization, strong communication and collaboration skills.
Ansys HFSS, Cadence EMX
2mo
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Senior ASIC Verification Engineer
Durham or Madison or Hillsboro
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelors/Masters in EE/CS/CE or equivalent, 5+ years verification experience, strong SystemVerilog and C/C++ skills, verification methodology experience (UVM, constrained-random, coverage, assertions), familiarity with VCS/IES and debug tools.
SystemVerilog, C, C++, VCS, IES, Debussy, GDB, Universal Verification Methodology (UVM), Semiformal Verification (SFV), Perl, Python
1w
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ASIC Physical Design Lead
Columbus or Fayetteville or Portland or Dayton
HybridFull Time
8+ YOE8+ years ASIC physical design experience with multiple tapeouts, advanced-node PnR, floorplanning, CTS, STA/timing closure, UPF/CPF low-power flows, and strong cross-functional communication.
Cadence, Synopsys, GDSII, UPF, CPF
1w
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EDA Tools SW Engineer
Hillsboro or Santa Clara or Austin or Phoenix
$174k-$330k/yr HybridFull Time
6+ YOEBS+10/ MS+8/ PhD+6 in Electrical/Computer Engineering or related,6+ years relevant experience, technical leadership, foundry/process/ASIC physical design and verification knowledge.
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Implant Software Staff Engineer (62275)
Lake Oswego, Oregon, United States
OnsiteFull Time
8+ YOE8+ years embedded software experience, BS/MS in engineering, experience with 8-bit microcontrollers, C and assembly, medical device/regulatory experience, strong communication and problem-solving.
C, Assembly, RTOS, ASIC
2mo
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Principal Logic Design Engineer
Hillsboro, Oregon, United States
$127k-$237k/yr HybridFull Time
8+ YOEExpertise in System Verilog/Verilog RTL, simulator experience (Questa/Incisive/VCS), scripting (Python/Perl/TCL), 8+–10+ years ASIC/FPGA logic design experience, strong communication and project management skills.
System Verilog, Verilog, Questa, Incisive, VCS, Python, Perl, TCL, UVM, AMBA AXI, CHI
2mo
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Product Engineer - Tessent Design for Test (DFT)
Wilsonville, Oregon, United States
$35-$64/hr HybridFull Time
1+ YOEBachelors in EE/CS/CE required, 1+ years DFT or ASIC experience preferred. Proficiency in Linux/Windows and scripting (TCL or Python). Strong problem-solving, communication, and ability to work as an individual contributor. Some domestic and international travel.
Linux, Microsoft Windows, TCL, Python, Tessent, Verilog, SystemVerilog, VHDL, ATPG, IEEE 1687
1mo
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Integrated Circuit Design Verification Engineer
Vancouver, Washington, United States
$173k-$259k/yr OnsiteFull Time
10+ YOE10+ years ASIC design verification experience; strong UVM/SystemVerilog skills; Siemens Questa; develop UVM/assertion testbenches, functional and code coverage, scripting/automation in Linux.
UVM, SystemVerilog, Siemens Questa, TCL, Make, Perl, Python, Shell, Linux
3w
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Field Applications Engineering
San Jose or Hillsboro
FieldFull Time
7+ YOE7+ years FPGA/ASIC design experience with VHDL/Verilog/SystemVerilog and tools like Radiant, Diamond, Quartus, or Vivado; Bachelor's in Electrical Engineering; strong presentation and customer-facing skills; available to travel periodically.
VHDL, Verilog, SystemVerilog, Radiant, Diamond, Quartus, Vivado
2mo
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Field Applications Engineering
San Jose or Hillsboro
OnsiteFull Time
7+ YOE7+ years FPGA/ASIC design experience with VHDL/Verilog/SystemVerilog and tool experience (Radiant, Diamond, Quartus, Vivado); Bachelor's in Electrical Engineering; strong communication and presentation skills; customer-facing experience and periodic travel availability.
VHDL, Verilog, SystemVerilog, Radiant, Diamond, Quartus, Vivado
4d
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Principal Firmware Architect
Redmond or Mountain View or Austin or Hillsboro
$143k-$275k/yr HybridFull Time
3+ YOERequires a degree in engineering or computer science and 3–8+ years of technical engineering experience depending on degree; preferred embedded software, firmware architecture, hardware interfaces, and security experience.
PCIe, I2C, eMMC, SPI, USB, UART, BMC, ASIC, SoC
4w
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FPGA Engineering Manager (Nextest, Tualatin, OR)
Tualatin, Oregon, United States
$171k-$274k/yr OnsiteFull Time
12+ YOE5+ MgmtB.S./M.S. in EE,12+ years digital ASIC/FPGA design,5+ years project lead,verilog/RTL,Cadence and static timing tools,PCIe/DDR/AXI/SERDES experience,excellent communication and presentation skills.
verilog, RTL, Cadence, Vivado, Quartus, UVM, Linux, Windows, PCIe, DDR3, DDR4, DDR5, AXI, Ethernet, SPI, SERDES, Lint, CDC, ATE
1mo
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Technical Director - Digital IC Design
San Jose or Hillsboro
$170k-$340k/yr OnsiteFull Time
12+ YOEBachelor's in EE/CE required (Master's/PhD preferred), 12+ years in digital IC design with hardware DSP focus, proven ASIC/SoC delivery, team leadership, RTL (Verilog/SystemVerilog/SystemC), synthesis/timing/simulation, FPGA prototyping, low-power and physical design expertise.
Verilog, SystemVerilog, SystemC, JasperGold
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