5 asic engineer jobs at 2 companies in Spring Lake, NC
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Senior Principal Engineer, Architecture ASIC / System
Toronto or Ottawa or Burlington or Irvine or Morrisville or Santa Clara or Westborough
$192k-$255k/yr OnsiteFull Time
14+ YOESenior architect with 14+ years in system architecture for SoC; expertise in interconnects, memory hierarchies, power management, security; strong technical leadership.
IP evaluation, IP block, SoC architecture
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ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead (Remote)
San Jose or Research Triangle Park or Acton or Dallas or Tempe or Cary or Carlsbad or Colorado Springs
$184k-$264k/yr RemoteFull Time
3+ YOEBachelor's/MS/PhD in Electrical Engineering with 3+ to 8+ years SI/PI experience; expertise in high-speed design, SI/PI simulation, layout review, SPICE; mentoring and leadership experience.
Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, Ansys EM, SPICE, Vector Network Analysis, IBIS
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Senior Principal Engineer, Design Verification
Morrisville, North Carolina, United States
$184k-$273k/yr OnsiteFull Time
12+ YOEDegree in CS/EE or related plus 12+ to 20+ years of ASIC verification experience; strong ASIC verification methodology, SoC/emulation/lab bring-up experience, leadership and communication skills.
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Staff Engineer, Design Verification
Morrisville, North Carolina, United States
$115k-$170k/yr OnsiteFull Time
12+ YOEExtensive ASIC verification experience leading DV architecture, emulation, post-silicon validation and delivery; strong leadership, communication, and cross-functional skills. Advanced degree plus many years of related experience required.
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Principal Technical Engineer 3rd Party IP Engineer
Morrisville or Austin or New York or Burlington or Westborough or Boise
$152k-$225k/yr OnsiteFull Time
3+ YOEBachelor’s in CS/EE with 5-10 years or Master/PhD with 3-5 years; deep DDR/LPDDR/GDDR/HBM/eMMC interface knowledge, ASIC design flow experience, 3rd-party IP management, project and customer communication skills.
DDR, LPDDR, GDDR, HBM, eMMC, logic synthesis, physical design, timing, DRC/LVS, Formal verification, Design-For-Test, DFT