4 asic engineer jobs at 2 companies in Vandergrift, PA
1d
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Applications Engineer - Silicon IP
San Jose or Pittsburgh or Austin
$160k-$210k/yr FieldFull Time
5+ YOEBS/MS in a relevant field and 5+ years in ASIC/SoC verification, physical design, silicon IP integration, or applications engineering; scripting, automation, and customer-facing technical expertise required.
Python, TCL, Make, SystemVerilog, UVM, Xcelium, VCS, Questa, Cadence Innovus, Synopsys ICC2, Fusion Compiler, PrimeTime, Tempus, Liberty, ECSM, CCS, LEF, SDC, UPF, STA, IR/EM, DRC/LVS
1mo
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Staff Verification Engineer
Pittsburgh, Pennsylvania, United States
$120k-$200k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC verification experience, Bachelor’s or Master’s in electrical/computer engineering, expertise in SystemVerilog/UVM, constrained-random and assertion verification, scripting in Python/Perl/Tcl/shell, Cadence/Mentor/Synopsys tool experience, protocol knowledge (Ethernet, PCIe, CXL, AMBA).
SystemVerilog, UVM, Python, Perl, Tcl, shell, Cadence, Mentor, Synopsys
1mo
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Sr. Staff Digital Design Engineer
Pittsburgh, Pennsylvania, United States
$140k-$230k/yr OnsiteFull Time
10+ YOE10+ years experience with digital ASIC/RTL design, Verilog/SystemVerilog, networking protocols (Ethernet, PCIe, CXL, UCIe, UALink), Unix/Linux scripting, Cadence/Mentor/Synopsys tool experience, strong technical leadership and debugging skills.
Verilog, SystemVerilog, Perl, Tcl, Python, Shell, Cadence, Mentor, Synopsys, UVM
2w
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Hardware Technical Program Manager
San Jose or Pittsburgh or Austin
$200k-$240k/yr OnsiteFull Time
7+ YOEBachelor’s degree in engineering or computer science; 7+ years in semiconductor or hardware engineering/program management; two SoC/ASIC programs through tapeout and silicon bring-up; chip design flow expertise.
Jira, Confluence, Microsoft Project, Smartsheet, Synopsys, Cadence, Siemens