18 asic engineer jobs at 5 companies in Ware, MA
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ASIC Physical Design Engineer
Maynard or Austin
$136k-$195k/yr HybridFull Time
5+ YOEBachelors in Engineering with 5+ years or Masters in Engineering with 3+ years in ASIC physical design; experience with floorplanning, place-and-route, STA, timing closure, DFT collaboration, scripting, and design flow optimization.
Cadence Innovus, Synopsys ICC2, Synopsys DC/FC, Synopsys Formality, Cadence LEC, Tempus, Python, TCL, Perl
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Senior ASIC Front End Infrastructure Engineer
Santa Clara or Westford or Austin or Durham
$184k-$357k/yr OnsiteFull Time
8+ YOE8+ years experience; Masters in Electrical Engineering, Computer Engineering, Computer Science or related; Python/Perl; AI tooling; Make; CI (Jenkins); strong problem solving; ASIC/CPU verification knowledge.
Python, Perl, Make, Jenkins
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Senior ASIC Timing Engineer
Westford or Durham
$168k-$311k/yr OnsiteFull Time
4+ YOEBS in ECE (8+ yrs) or MS (4+ yrs) in synthesis and timing; hands-on STA, timing constraints, ECOs, physical design and synthesis/LEC; experience with Synopsys PrimeTime or Cadence Tempus; Python, Tcl, Make scripting.
Synopsys PrimeTime, Cadence Tempus, Python, Tcl, Make
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Senior ASIC Hardware Design Engineer
Westford, Massachusetts, United States
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelor's or Master's in EE/CE/CS (or equivalent) with 5+ years industry experience; strong Verilog/SystemVerilog and RTL/microarchitecture experience; scripting in Perl or Python; understanding of physical implementation and VLSI.
Verilog, SystemVerilog, Perl, Python
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Senior ASIC Hardware Design Engineer
Westford, Massachusetts, United States
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelors in EE/CE/CS (or equivalent) and 5+ years experience; strong Verilog/SystemVerilog skills, RTL/micro-architecture experience, Python/Perl scripting, understanding of physical implementation and VLSI.
Verilog, SystemVerilog, Perl, Python
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Senior ASIC Verification Engineer, Coherent High Speed Interconnect
Santa Clara or Austin or Westford or Hillsboro
$136k-$265k/yr HybridFull Time
3+ YOEBachelors/Masters (or equivalent), 3+ years verification experience, SystemVerilog/UVM, C++, testbench architecture, PCIe/CXL/CHI familiarity, VCS/Debussy/GDB exposure, strong debugging and mentoring skills.
SystemVerilog, UVM, C++, VCS, Debussy, GDB, PCIe, CXL, CHI
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Senior ASIC Front End Infrastructure Engineer
Santa Clara or Durham or Austin or Westford
$184k-$357k/yr OnsiteFull Time
8+ YOEMaster's degree (or equivalent) in EE/CE/CS, 8+ years relevant experience, Python/Perl programming, CI/build system experience (Make, Jenkins), AI tooling experience, verification domain knowledge, strong debugging and problem-solving skills.
Python, Perl, Make, Jenkins, containers
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Senior Principal Engineer, Architecture ASIC / System
Toronto or Ottawa or Burlington or Irvine or Morrisville or Santa Clara or Westborough
$192k-$255k/yr OnsiteFull Time
14+ YOESenior architect with 14+ years in system architecture for SoC; expertise in interconnects, memory hierarchies, power management, security; strong technical leadership.
IP evaluation, IP block, SoC architecture
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ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead (Remote)
San Jose or Research Triangle Park or Acton or Dallas or Tempe or Cary or Carlsbad or Colorado Springs
$184k-$264k/yr RemoteFull Time
3+ YOEBachelor's/MS/PhD in Electrical Engineering with 3+ to 8+ years SI/PI experience; expertise in high-speed design, SI/PI simulation, layout review, SPICE; mentoring and leadership experience.
Cadence Sigrity, Ansys HFSS, Keysight ADS, Cadence APD, Ansys EM, SPICE, Vector Network Analysis, IBIS
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Aircraft Structural Dynamics Engineer
Wichita or Tucson or Opa-locka or Fort Worth or Windsor
OnsiteFull Time
15+ YOEUniversity engineering degree, 15+ years technical experience (10+ in aeronautics), 5+ years FPGA/ASIC or embedded software, knowledge of airborne software/hardware standards, DOORS/JAMA experience, C/C++/Ada95/Assembly/Python, OIQ membership preferred.
DOORS, JAMA, C, C++, Ada95, Assembly, Python
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Senior Electrical Engineer - FPGA Design
Tewksbury or Marlborough
$87k-$165k/yr OnsiteFull Time
5+ YOEU.S. citizen able to obtain/maintain Secret clearance; STEM bachelor's degree typically required; minimum 5 years relevant FPGA/ASIC design or verification experience with VHDL/Verilog/SystemVerilog; experience with Xilinx or Microsemi devices and integration/debug.
VHDL, Verilog, SystemVerilog, UVM, Xilinx, Microsemi, Veloce, ARM, MicroBlaze, Nios
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Principal Technical Engineer 3rd Party IP Engineer
Morrisville or Austin or New York or Burlington or Westborough or Boise
$152k-$225k/yr OnsiteFull Time
3+ YOEBachelor’s in CS/EE with 5-10 years or Master/PhD with 3-5 years; deep DDR/LPDDR/GDDR/HBM/eMMC interface knowledge, ASIC design flow experience, 3rd-party IP management, project and customer communication skills.
DDR, LPDDR, GDDR, HBM, eMMC, logic synthesis, physical design, timing, DRC/LVS, Formal verification, Design-For-Test, DFT
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Senior Memory Controller Verification Engineer
Santa Clara or Austin or Westford or Hillsboro or Seattle
$168k-$311k/yr HybridFull Time
6+ YOE6+ years ASIC verification experience, SystemVerilog/UVM, simulation and debug tool experience (VCS, Debussy, GDB), strong C/C++ and scripting (Python/Perl/shell), BS/MS or equivalent.
VCS, Debussy, GDB, System Verilog, UVM, C, C++, Python, Perl, shell
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Senior Memory Controller Verification Engineer
Santa Clara or Westford or Austin or Hillsboro or Seattle
$168k-$311k/yr HybridFull Time
6+ YOE6+ years ASIC verification experience, BS/MS or equivalent, SystemVerilog/UVM experience, familiarity with VCS/Debussy/GDB, C/C++ and scripting (Python/Perl/shell), strong debugging and teamwork skills.
VCS, Debussy, GDB, System Verilog, UVM, C, C++, Python, Perl, Shell
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Hardware & Silicon Validation Senior Staff Engineer
Westborough or Santa Clara
$143k-$212k/yr OnsiteFull Time
3+ YOEBachelor's (or Master's/PhD) in CS/EE,3+ years (Master's) or 5+ years (Bachelor's) validating SoCs/ASICs, hands-on lab debugging, high-speed interfaces, scripting (Python/Perl/Shell), C/C++, and Linux.
oscilloscope, logic analyzer, protocol analyzer, FPGA, Python, Perl, Shell, C, C++, Linux
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Senior Network Solution Engineer (Weekend Coverage)
Santa Clara or Westford or Austin or Durham or Redmond or New York
$140k-$270k/yr OnsiteFull Time
5+ YOE5+ years software development (C, C++, Python, or Go) in the networking industry, 5+ years supporting in-field production network equipment, bachelor's degree or equivalent, experience with Linux NIC drivers/ASICs/firmware/network OS, expert Ethernet/IP knowledge.
C, C++, Python, Go, Linux, InfiniBand, NVLink, Spectrum-X
6d
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Senior Architect, NVLink
Westford, Massachusetts, United States
$184k-$357k/yr OnsiteFull Time
8+ YOEMS/PhD or equivalent, 8+ years in architecture/design/verification, ASIC design experience, shipped projects in processor and I/O architecture, programming in C++ and Verilog, strong communication and initiative.
C++, Verilog
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Senior Architect, NVLink
Westford, Massachusetts, United States
$184k-$357k/yr OnsiteFull Time
8+ YOEMS/PhD in EE/CS/CE or equivalent experience,8+ years in architecture/design/verification,ASIC and processor/I/O architecture experience,programming in C++ and Verilog,history of shipped projects.
C++, Verilog
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