42 asic engineer jobs at 17 companies in Webster, MA
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Project Lead ASIC Engineer
Cambridge, Massachusetts, United States
$95k-$245k/yr HybridFull Time
5+ YOEBachelor's in engineering required (masters preferred); 5+ years ASIC hardware engineering experience with bachelor's (less with advanced degrees); ability to design/simulate transistor-level circuits, lead small teams, and work with fabrication/test sites.
2mo
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ASIC Physical Design Engineer
Maynard or Austin
$136k-$195k/yr HybridFull Time
5+ YOEBachelors in Engineering with 5+ years or Masters in Engineering with 3+ years in ASIC physical design; experience with floorplanning, place-and-route, STA, timing closure, DFT collaboration, scripting, and design flow optimization.
Cadence Innovus, Synopsys ICC2, Synopsys DC/FC, Synopsys Formality, Cadence LEC, Tempus, Python, TCL, Perl
2mo
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ASIC/FPGA Verification Engineer IV
Denver or Highlands Ranch or Sunnyvale or Cambridge
$124k-$246k/yr OnsiteFull Time
5+ YOEBachelors in EE (or equivalent), 5+ years FPGA/ASIC verification experience, UVM/SystemVerilog/VHDL/Verilog expertise, experience with modern verification methodologies and tools, and ability to obtain DoD Secret clearance (US citizenship required).
SystemVerilog, Universal Verification Methodology (UVM), VHDL, Verilog, Linux, Microsoft Project, JIRA, Python, OVM, VMM
2mo
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Senior ASIC Front End Infrastructure Engineer
Santa Clara or Westford or Austin or Durham
$184k-$357k/yr OnsiteFull Time
8+ YOE8+ years experience; Masters in Electrical Engineering, Computer Engineering, Computer Science or related; Python/Perl; AI tooling; Make; CI (Jenkins); strong problem solving; ASIC/CPU verification knowledge.
Python, Perl, Make, Jenkins
2mo
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Staff Engineer, Digital ASIC Design (CONTRACT)
Burlington or New York
HybridContract
8+ YOEBS/MS/PhD in EE/CE; 8+ yrs in digital IC/ASIC/SoC; RTL ownership; SystemVerilog/Verilog; high-throughput datapaths; silicon constraints; SV/UVM; Python/cocotb; post-silicon bring-up.
SystemVerilog/Verilog, UVM, Python, cocotb, RTL, RTL verification, Fixed-point modeling
2mo
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Senior ASIC Timing Engineer
Westford or Durham
$168k-$311k/yr OnsiteFull Time
4+ YOEBS in ECE (8+ yrs) or MS (4+ yrs) in synthesis and timing; hands-on STA, timing constraints, ECOs, physical design and synthesis/LEC; experience with Synopsys PrimeTime or Cadence Tempus; Python, Tcl, Make scripting.
Synopsys PrimeTime, Cadence Tempus, Python, Tcl, Make
3mo
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Mixed Signal ASIC Engineer
Boston, Massachusetts, United States
OnsiteFull Time
5+ YOEPhD in electrical engineering or equivalent industry experience; 5+ years designing analog/mixed-signal ICs; strong ADC/DAC, amplifiers; tape-out experience; Cadence or Synopsys tools; end-to-end IC development.
Cadence, Synopsys
2mo
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Senior Principal Engineer, Architecture ASIC / System
Toronto or Ottawa or Burlington or Irvine or Morrisville or Santa Clara or Westborough
$192k-$255k/yr OnsiteFull Time
14+ YOESenior architect with 14+ years in system architecture for SoC; expertise in interconnects, memory hierarchies, power management, security; strong technical leadership.
IP evaluation, IP block, SoC architecture
1mo
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Electrical Engineer - Hardware & Embedded Systems
Waltham, Massachusetts, United States
$100k-$116k/yr OnsiteFull Time
4+ YOEBachelor's in electrical/computer engineering, 4+ years relevant experience, 3+ years embedded systems, proficiency in Embedded C/C++, RTOS, hardware-software integration, control systems, and communication protocols (I2C, SPI, UART, CAN).
Embedded C/C++, RTOS, I2C, SPI, UART, CAN, MATLAB/Simulink, LabVIEW, PLCs, FPGA, ASIC, Git, IDEs, debuggers
2mo
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Staff Design Verification Engineer – Coherent Interconnect
Boston or Austin
OnsiteFull Time
7+ YOEBS/ MS in Electrical/Computer Engineering; 7+ years ASIC/SoC verification; strong CXL/CHI/AXI; SystemVerilog/UVM; cache-coherent systems; test plans, coverage; Python scripting.
SystemVerilog, UVM, Python
2w
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Aircraft Structural Dynamics Engineer
Wichita or Tucson or Opa-locka or Fort Worth or Windsor
OnsiteFull Time
15+ YOEUniversity engineering degree, 15+ years technical experience (10+ in aeronautics), 5+ years FPGA/ASIC or embedded software, knowledge of airborne software/hardware standards, DOORS/JAMA experience, C/C++/Ada95/Assembly/Python, OIQ membership preferred.
DOORS, JAMA, C, C++, Ada95, Assembly, Python
2w
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Sr. Design for Test (DFT) Engineer
Toronto or Mountain View or Boston
HybridFull Time
13+ YOEBachelor's in Electrical Engineering, 13+ years DFT experience on ASICs, 2+ tapeouts, experience with DFT CAD/ATPG, Python/TCL scripting, post-silicon bring-up and ATE interfacing.
Python, TCL, SystemVerilog, ATPG, ATE
1mo
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Engineer: Sr. Electrical Design Engineer
Cambridge, Massachusetts, United States
$80k-$110k/yr OnsiteFull Time
5+ YOEMaster's in EE, 5+ years product development experience, PCB and embedded hardware design, Altium/Eagle, C/Assembly, verification/validation, FDA/ISO 13485 experience, LabVIEW/MATLAB/Simulink familiarity.
Altium, Autodesk Eagle, C, Assembly, Verilog, VHDL, FPGA, ASIC, LabVIEW, MATLAB, Simulink, Java, Android, oscilloscopes, logic analyzers
1mo
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FPGA Design Engineer II
Needham, Massachusetts, United States
$129k-$166k/yr OnsiteFull Time
3+ YOEBS/MS in related field, 3+ years FPGA/ASIC digital logic design, proficiency in SystemVerilog or VHDL, experience with simulation/debug tools (VCS, Verdi), Linux, strong debugging and communication skills.
SystemVerilog, VHDL, VCS, Verdi, Linux, C, Python, Perl, PCIe, Ethernet, DDR
2mo
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Senior Electrical Engineer - FPGA Design
Tewksbury or Marlborough
$87k-$165k/yr OnsiteFull Time
5+ YOEU.S. citizen able to obtain/maintain Secret clearance; STEM bachelor's degree typically required; minimum 5 years relevant FPGA/ASIC design or verification experience with VHDL/Verilog/SystemVerilog; experience with Xilinx or Microsemi devices and integration/debug.
VHDL, Verilog, SystemVerilog, UVM, Xilinx, Microsemi, Veloce, ARM, MicroBlaze, Nios
1w
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Staff Engineer, Digital Design Engineering
Chelmsford, Massachusetts, United States
$135k-$202k/yr OnsiteFull Time
8+ YOEExpertise in FPGA/ASIC RTL and schematic capture, board-level design, high-speed interfaces, Verilog/VHDL, simulation, and collaboration; U.S. citizenship and ability to obtain Secret clearance required; preferred 8+ years digital design experience.
Verilog, VHDL, 100 GigE, Aurora, PCIe, Allegro, PADS, C#, Python, C/C++, TCL
2mo
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Member of Technical Staff, Formal Verification
Santa Clara or Boston
OnsiteFull Time
10+ YOEBachelor's or Master's in EE/CE, 10+ years ASIC/SoC verification with 7+ years formal verification, expertise in SVA and formal tools, scripting (Tcl/Python/Perl/Shell), strong debugging and leadership skills.
SystemVerilog Assertions (SVA), Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, UVM, Tcl, Python, Perl, Shell
3w
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Director of Business Development
Boston or United States
RemoteFull Time
8+ YOE8+ years selling engineering or semiconductor services, Bachelor's degree or equivalent, ability to sell turnkey design and onshore staffing, technical competency in electronic design, familiarity with defense/secure verticals preferred.
AMD, Altera, Intel, Xilinx, FPGA, ASIC
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