6 asic engineer jobs at 4 companies in West Warwick, RI
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ASIC Physical Design Engineer
Maynard or Austin
$136k-$195k/yr HybridFull Time
5+ YOEBachelors in Engineering with 5+ years or Masters in Engineering with 3+ years in ASIC physical design; experience with floorplanning, place-and-route, STA, timing closure, DFT collaboration, scripting, and design flow optimization.
Cadence Innovus, Synopsys ICC2, Synopsys DC/FC, Synopsys Formality, Cadence LEC, Tempus, Python, TCL, Perl
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Senior Principal Engineer, Architecture ASIC / System
Toronto or Ottawa or Burlington or Irvine or Morrisville or Santa Clara or Westborough
$192k-$255k/yr OnsiteFull Time
14+ YOESenior architect with 14+ years in system architecture for SoC; expertise in interconnects, memory hierarchies, power management, security; strong technical leadership.
IP evaluation, IP block, SoC architecture
1mo
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Electrical Engineer - Hardware & Embedded Systems
Waltham, Massachusetts, United States
$100k-$116k/yr OnsiteFull Time
4+ YOEBachelor's in electrical/computer engineering, 4+ years relevant experience, 3+ years embedded systems, proficiency in Embedded C/C++, RTOS, hardware-software integration, control systems, and communication protocols (I2C, SPI, UART, CAN).
Embedded C/C++, RTOS, I2C, SPI, UART, CAN, MATLAB/Simulink, LabVIEW, PLCs, FPGA, ASIC, Git, IDEs, debuggers
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FPGA Design Engineer II
Needham, Massachusetts, United States
$129k-$166k/yr OnsiteFull Time
3+ YOEBS/MS in related field, 3+ years FPGA/ASIC digital logic design, proficiency in SystemVerilog or VHDL, experience with simulation/debug tools (VCS, Verdi), Linux, strong debugging and communication skills.
SystemVerilog, VHDL, VCS, Verdi, Linux, C, Python, Perl, PCIe, Ethernet, DDR
2w
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Principal Technical Engineer 3rd Party IP Engineer
Morrisville or Austin or New York or Burlington or Westborough or Boise
$152k-$225k/yr OnsiteFull Time
3+ YOEBachelor’s in CS/EE with 5-10 years or Master/PhD with 3-5 years; deep DDR/LPDDR/GDDR/HBM/eMMC interface knowledge, ASIC design flow experience, 3rd-party IP management, project and customer communication skills.
DDR, LPDDR, GDDR, HBM, eMMC, logic synthesis, physical design, timing, DRC/LVS, Formal verification, Design-For-Test, DFT
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Hardware & Silicon Validation Senior Staff Engineer
Westborough or Santa Clara
$143k-$212k/yr OnsiteFull Time
3+ YOEBachelor's (or Master's/PhD) in CS/EE,3+ years (Master's) or 5+ years (Bachelor's) validating SoCs/ASICs, hands-on lab debugging, high-speed interfaces, scripting (Python/Perl/Shell), C/C++, and Linux.
oscilloscope, logic analyzer, protocol analyzer, FPGA, Python, Perl, Shell, C, C++, Linux