6d
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Lead ASIC Digital Design Engineer
Annapolis Junction or Telework or Boise or Salt Lake City or Bloomington
$177k-$187k/yr RemoteFull Time
8+ YOE8+ years ASIC/FPGA RTL design experience, ASIC tape-out and timing-closure experience, familiarity with FinFET nodes and commercial foundry flows, EDA tool and JIRA proficiency, strong RTL and microarchitecture skills.
JIRA, Microsoft Office
1w
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Senior Principal ASIC FPGA Engineer
Boise or United States
$191k-$212k/yr HybridFull Time
10+ YOEBachelor's (or Master's) in ECE or related plus 8–10+ years ASIC/FPGA experience, DoD Secret clearance, RTL and timing-closure expertise, FinFET and foundry flow experience, JIRA and Microsoft Office proficiency.
JIRA, Microsoft Office
1w
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Senior ASIC Digital Design Engineer
Annapolis Junction or Boise or Salt Lake City or Bloomington or United States
$142k-$150k/yr RemoteFull Time
5+ YOEBachelor's in ECE or related and 5+ years experience (or Master's+3); US citizenship and ability to obtain DoD Secret clearance; strong RTL/ASIC design and verification experience.
JIRA, Microsoft Office
2mo
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HIG Product Engineer - Media Health
Boise, Idaho, United States
OnsiteFull Time
Master's in Computer or Electrical Engineering or related field; digital circuit design, ASIC testing with scan tools, Python and C; Linux; bench testing; BIST/APG memory testing.
Python, C, Linux, Verilog, SPICE, JMP
6d
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Principal Technical Engineer 3rd Party IP Engineer
Morrisville or Austin or New York or Burlington or Westborough or Boise
$152k-$225k/yr OnsiteFull Time
3+ YOEBachelor’s in CS/EE with 5-10 years or Master/PhD with 3-5 years; deep DDR/LPDDR/GDDR/HBM/eMMC interface knowledge, ASIC design flow experience, 3rd-party IP management, project and customer communication skills.
DDR, LPDDR, GDDR, HBM, eMMC, logic synthesis, physical design, timing, DRC/LVS, Formal verification, Design-For-Test, DFT