10 asic physical design engineer jobs at 5 companies in Los Angeles, CA
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ASIC Engineer, Physical Design Engineer
Aliso Viejo, California, United States
OnsiteFull Time
5+ YOERequires 5+ years of experience, physical design and timing closure expertise, EDA tool experience, floorplanning, place and route, power and clock distribution, timing convergence, and U.S. citizenship.
Perl, Tcl, Innovus, ICC2, PrimeTime, RedHawk, Voltus, Calibre, EDA
2mo
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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine or Austin or Sunnyvale
$160k-$220k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical engineering, computer engineering or computer science; 5+ years ASIC/physical design experience; strong EDA tool knowledge; scripting skills; ability to work extended hours.
EDA tools, Python, Csh/Bash/Shell, Perl, TCL, Makefile
2mo
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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Austin or Irvine or Sunnyvale
$170k-$230k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical, computer engineering or computer science; 5+ years ASIC/physical design flow development; strong RTL2GDSII, EDA tools; DFT/MBIST; scripting (Python, TCL, Perl, Bash).
RTL2GDSII, EDA tools, Python, TCL, Perl, Bash, Makefile
2mo
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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Austin or Irvine or Sunnyvale
OnsiteFull Time
5+ YOEBachelor's in electrical/computer engineering or computer science; 5+ years ASIC/physical design experience; RTL2GDSII, EDA tools; scripting; ITAR awareness.
EDA tools, RTL2GDSII, Python, TCL, Perl, Shell
3d
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Principal Physical Design Engineer
San Jose or Irvine
$150k-$250k/yr OnsiteFull Time
5+ YOE5+ years of ASIC physical design experience, advanced-node tapeout expertise, EDA tool proficiency, and expertise in synthesis, power analysis, EM/IR cleanup, timing closure, and physical verification.
System-on-Chips (SoCs), RTL, GDSII, Static Timing Analysis (STA), Design Rule Checking (DRC), Layout Versus Schematic (LVS), Tcl, Python, Perl, Cadence Innovus, Cadence Tempus, Cadence Voltus, Cadence Pegasus, Calibre
3mo
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FPGA/ASIC Design Engineer (Silicon Engineering)
Irvine or Redmond
$125k-$145k/yr OnsiteFull Time
1+ YOEBachelor’s in EE/CE/CS/Physics; 1+ years RTL design (SystemVerilog/Verilog/VHDL); strong Python/C/C++, and PCB/lab experience.
Verilog/SystemVerilog, VHDL, Python, C/C++, Bash, HDL simulators, Spyglass, Vivado, Quartus, AXI/APB/AHB protocols
2mo
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Senior Custom ASIC Engineering Lead
San Jose or Fort Collins or Irvine
$144k-$230k/yr OnsiteFull Time
10+ YOEExtensive ASIC physical design and STA experience, multiple tape-outs in advanced nodes, EDA tool and scripting (Tcl, shell) proficiency, knowledge of low-power design, and ability to manage customer ASIC programs. Bachelors+12 yrs or Masters+10 yrs required.
EDA, Tcl, Shell, Verilog
2mo
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Senior Custom ASIC Engineering Lead
San Jose or Fort Collins or Irvine
$144k-$230k/yr OnsiteFull Time
10+ YOE10+ years semiconductor ASIC experience, multiple tape-outs, hands-on physical design/STA/DFT experience, Tcl/shell/Verilog scripting, knowledge of low-power design and PPA tradeoffs; Bachelor's or Master's degree required.
EDA, Tcl, Shell, Verilog
2mo
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Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Irvine or Austin or Sunnyvale
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in electrical/computer engineering or computer science; 5+ years ASIC/physical design flow experience; strong DRC/LVS/ESD, Calibre/IC Validator/Pegasus proficiency; advanced node experience; scripting (Python, Perl, TCL, Bash).
Calibre, IC Validator, Pegasus, DFT, Python, Perl, TCL, Bash, Makefile
20h
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Sr. Manager - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning
Cupertino or Los Angeles County
$240k-$324k/yr OnsiteFull Time
3+ YOEBachelor's, master's, or doctoral degree in EE/CS; 7+ years ASIC and communications experience; 3+ years static timing analysis and constraint development; expertise with EDA tools, physical design, and automation.
ASIC, EDA, PrimeTime, Tempus, PT-DMSA, Tempus-ECO, Tweaker, STAR-RC, Quantus, SPICE, SPECTRE, UVM, C, SystemC, MATLAB, Python, Embedded C, C++, Agile, TDD, BDD, CI, Git, CI/CD, SPI, I2C, I3C, UART, OFDMA, TDMA, CDMA, WiMAX, 802.11ad, DVB-S2, DVB-C, SoCs, FPGAs, NVIC, DFT