3w
Save
Mark Applied
Hide
Senior ASIC Physical Design Engineer
United States
$170k-$250k/yr RemoteFull Time
5+ YOEBachelor's or Master's in EE/Computer Engineering, 5+ years ASIC physical design experience, hands-on with Synopsys ICC2/Fusion Compiler or Cadence Innovus, timing/power/physical verification expertise, DFT and power-intent knowledge.
Synopsys ICC2, Synopsys Fusion Compiler, Cadence Innovus, GDSII, DRC, LVS, IR drop, EM, CTS, STA, DFT, UPF, CPF, TSMC
2w
Save
Mark Applied
Hide
Senior ASIC Physical Design Engineer
Sunnyvale, California, United States
$163k-$237k/yr OnsiteFull Time
7+ YOEBachelor's degree or equivalent,7+ years physical design experience, proficiency in Python/Tcl/Perl, experience with STA and Synopsys/Cadence PnR tools, ASIC backend flows and DFT knowledge.
Python, Tcl, Perl, Synopsys, Cadence, Static Timing Analysis (STA)
2mo
Save
Mark Applied
Hide
Principal Engineer, ASIC Physical Design
Minneapolis, Minnesota, United States
OnsiteFull Time
15+ YOE15+ years ASIC physical design experience, bachelor's or master's in EE/electronics/computer architecture, production tape-outs, UPF/CPF low-power expertise, scripting in Tcl/Perl/Python, Synopsys/Cadence/Calibre experience.
Synopsys, Cadence, Calibre, Tcl, Perl, Python, UPF, CPF
2mo
Save
Mark Applied
Hide
ASIC Physical Design Engineer
New York, New York, United States
$250k-$300k/yr OnsiteFull Time
Experience with physical design flows (floorplanning, place-and-route, timing closure, P&R, physical verification, power analysis); able to own a flow end-to-end; read/write RTL; cross-stack thinking; programming in Python, C++, or similar.
Python, C++, RTL, OCaml, Haskell
1mo
Save
Mark Applied
Hide
Senior ASIC Physical Design Engineer
San Jose or Austin or Research Triangle Park
$165k-$241k/yr OnsiteFull Time
1+ YOEDegree in Electrical or Computer Engineering with relevant ASIC experience (varies by degree), experience with EDA tools (Innovus, Tempus, PrimeTime, Redhawk, Voltus, Calibre, Pegasus), STA experience, and Python scripting.
Innovus, Tempus, PrimeTime, Redhawk, Voltus, Calibre, Pegasus, Tweaker, Static Timing Analysis (STA), Python, AI tools
2d
Save
Mark Applied
Hide
Senior ASIC Physical Design Engineer, Netlisting
Santa Clara or Austin
$136k-$265k/yr HybridFull Time
3+ YOE5+ years (BS) or 3+ years (MS) experience in physical ASIC design, expertise in equivalence checking/FV, RTL/logic design, CDC/MTBF analysis, logic synthesis, STA and timing convergence, and scripting/programming skills.
Perl, TCL, Make, Python, Static Timing Analysis (STA)
1mo
Save
Mark Applied
Hide
Senior ASIC Physical Design Engineer
Laurel, Maryland, United States
$105k-$290k/yr OnsiteFull Time
6+ YOEAssociate’s degree (or equivalent) in a technical field, 6+ years back-end ASIC design, skilled with Cadence back-end tools and Siemens Calibre, able to obtain Interim Secret and Secret clearance, US citizenship required.
Cadence ASIC design tools, Cadence Virtuoso, Siemens Calibre, Siemens ASIC design tools, DRC, DRC+, MCD, LVS
2mo
Save
Mark Applied
Hide
ASIC Physical Design Manager
Colorado Springs, Colorado, United States
$151k-$253k/yr OnsiteFull Time
7+ YOE5+ MgmtB.S. or M.S. in Electrical/Computer Engineering; 7+ years digital ASIC physical design; 5+ years project/program management; tapeout experience.
Place and Route, Timing analysis, DFT, Signoff tools, Physical design methodologies
3mo
Save
Mark Applied
Hide
ASIC Design Engineer
Irvine or Andover
$108k-$173k/yr OnsiteFull Time
6+ YOEBachelor's in Electrical Engineering with 8+ years of related experience or Master's in Electrical Engineering with 6+ years of related experience; ASIC implementation, synthesis, DFT, floorplanning, place & route, clocking, power planning and analysis, timing closure, signal integrity, physical design checks.
EDA tools, Synthesis tools, Place and Route (P&R) tools, Floorplanning tools, Clocking/Timing analysis tools, Power analysis tools
3w
Save
Mark Applied
Hide
ASIC Engineer, Physical Design
Sunnyvale or Austin
$178k-$250k/yr OnsiteFull Time
8+ YOEBachelor's degree (or equivalent) and 8+ years in ASIC physical design with end-to-end implementation, experience with industry EDA tools, static timing analysis and multi-corner closure at advanced nodes (7nm or below); scripting and low-power experience preferred.
Synopsys IC Compiler, Cadence Innovus, Primetime, Calibre, Python, Tcl
2d
Save
Mark Applied
Hide
ASIC Physical Design Engineer, Principal
United States or Canada
$150k-$300k/yr RemoteFull Time
12+ YOE12+ years physical design experience from floorplanning through tapeout, expert in Innovus/ICC2, timing/power/signoff, advanced-node tapeouts, and methodology development.
Innovus, ICC2, Tempus, PrimeTime, Voltus, RedHawk, Calibre
2mo
Save
Mark Applied
Hide
Sr. ASIC Design Engineer
Roseville, California, United States
$154k-$311k/yr OnsiteFull Time
5+ YOEDesign ASICs with Verilog/SystemVerilog, RTL, timing, verification; collaborate with verification and physical design; 5+ years of relevant experience.
Verilog, SystemVerilog, RTL, SVA, EDA tools, Python, Perl
1mo
Save
Mark Applied
Hide
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine or Austin or Sunnyvale
$160k-$220k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical engineering, computer engineering or computer science; 5+ years ASIC/physical design experience; strong EDA tool knowledge; scripting skills; ability to work extended hours.
EDA tools, Python, Csh/Bash/Shell, Perl, TCL, Makefile
2mo
Save
Mark Applied
Hide
Senior ASIC Design Engineer
Santa Clara, California, United States
$136k-$219k/yr HybridFull Time
3+ YOEBS in EE/CE required, 3+ years ASIC/logic design experience, Verilog/System-Verilog, multi-clock domain experience, Perl or Python scripting, physical design and VLSI knowledge, strong communication skills.
Verilog, System-Verilog, PERL, Python, Perl, Tcl, Make
1d
Save
Mark Applied
Hide
Senior Digital ASIC Design Engineer
Upton, New York, United States
$115k-$145k/yr OnsiteFull Time
7+ YOEBachelor's in EE/CE/applied physics, 7+ years digital ASIC design, SystemVerilog/Verilog RTL, CAD/EDA tool experience, strong timing/CDC/low-power knowledge, and collaboration with mixed-signal, verification, and firmware teams.
SystemVerilog, Verilog, Cadence, Synopsys, Siemens, AXI, AHB, APB, Wishbone, I2C, SPI, JTAG, Tcl, Python, Perl, Make, shell
4w
Save
Mark Applied
Hide
Staff. Physical Design Engineer
San Diego, California, United States
$140k-$210k/yr OnsiteFull Time
2+ YOEBachelor's in science/engineering +2 years ASIC design experience (or Master's +1 or PhD). Requires ASIC design/verification skills, experience with architecture/design and scripting tools, and strong communication.
RTL to GDS Flow, Virtuoso
2mo
Save
Mark Applied
Hide
ASIC Engineer 2
Longmont, Colorado, United States
$143k-$176k/yr OnsiteFull Time
Define ASIC design/verification requirements; HDL/RTL, scripting; physical design basics; review requirements and collaborate with architects.
Perl, Python, C, Unix shell, Verilog, SystemVerilog, VHDL, RTL
1w
Save
Mark Applied
Hide
Advanced ASIC Physical Design Lead (Teradyne, North Reading, MA)
North Reading, Massachusetts, United States
$192k-$308k/yr OnsiteFull Time
10+ YOE10+ years ASIC physical design experience at advanced nodes, RTL-to-GDSII expertise, STA and signoff knowledge, experience integrating high-speed IP, leadership and scripting skills.
Cadence, Tcl, Python, Make
2mo
Save
Mark Applied
Hide
Senior Physical Design Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
8+ YOESenior Physical Design Engineer with 8+ years in ASIC/SoC physical design; Cadence Innovus expertise; floorplanning, CTS, routing; timing closure; scripting (Python/Tcl).
Cadence Innovus, Synopsys ICC2, Mentor Calibre, Tcl, Python, Verilog, SystemVerilog, UVM, VHDL
2mo
Save
Mark Applied
Hide
Physical Design Engineer
Austin or Boulder or Chicago or London or New York City or Seattle
$200k-$300k/yr OnsiteFull Time
Experience in high-performance ASIC design; digital logic; DFT concepts; scripting (Python, Tcl, shell); static timing analysis; timing closure; Innovus/PrimeTime.
Innovus, PrimeTime, Python, Tcl, shell
Explore Jobs