68 asic verification engineer jobs at 16 companies in Austin, TX
2mo
Save
Mark Applied
Hide
Senior ASIC Verification Engineer
Austin, Texas, United States
$136k-$265k/yr HybridFull Time
5+ YOEBS/MS in Electrical or Computer Engineering (or equivalent), 5+ years design verification experience, UVM/SystemVerilog, ASIC flow, Perl or Python, familiarity with synthesis/simulation and debug tools.
SystemVerilog, UVM, Perl, Python, dc_shell, VCS, Debussy, GDB
2mo
Save
Mark Applied
Hide
ASIC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years verification experience, 2+ full block/system verification cycles, deep VLSI verification knowledge, experience with SystemVerilog/UVM/eRM, familiarity with data-paths/protocols (Ethernet preferred), mentoring and cross-team collaboration.
SystemVerilog, UVM, eRM, RTL, Ethernet
1d
Save
Mark Applied
Hide
ASIC Design Verification Engineer
Austin, Texas, United States
HybridFull Time
3+ YOESeveral years of industry RTL verification experience in IP, ASIC, or SoC; SystemVerilog and UVM expertise; testbench architecture; RTL debug; scripting; and a bachelor's or master's degree in electrical or computer engineering preferred.
SystemVerilog, UVM, TCL, Python, Perl, Linux, GIT, LSF
1mo
Save
Mark Applied
Hide
Senior ASIC Verification Engineer
Austin or Santa Clara
$136k-$265k/yr HybridFull Time
5+ YOEBachelors/Masters in CS/CE/EE (or equivalent experience), 5+ years experience, SystemVerilog OOP, verification methodology (UVM), VCS/Debussy/GDB exposure, experience with random stimulus, functional coverage, assertions, firmware/hardware verification.
SystemVerilog, VCS, Debussy, GDB, UVM, C, RISC-V Assembly
1d
Save
Mark Applied
Hide
ASIC Design Verification Engineer (784248)
Austin, Texas, United States
HybridFull Time
3+ YOESeveral years of industry RTL verification experience in IP, ASIC, or SoC; SystemVerilog and UVM expertise; testbench architecture; RTL debugging; scripting with TCL, Python, or Perl; and a bachelor's or master's degree in engineering or equivalent experience.
SystemVerilog, UVM, TCL, Python, Perl, Linux, GIT, LSF, AMBA APB, AXI, ACE-Lite, CHI
1mo
Save
Mark Applied
Hide
ASIC Engineer, Design Verification
Sunnyvale or Austin
$178k-$250k/yr OnsiteFull Time
8+ YOEBachelor's in CS/CE or equivalent, 8+ years SystemVerilog/UVM or C/C++ verification, IP/SoC verification experience, EDA and scripting (Python, TCL, Perl, Shell), experience with assertions, formal or emulation.
SystemVerilog, UVM, OVM, C, C++, Python, TCL, Perl, Shell
1mo
Save
Mark Applied
Hide
ASIC Design Verification Engineer
Austin, Texas, United States
$156k-$268k/yr OnsiteFull Time
Develop and execute IP verification architectures and test plans using System Verilog, UVM, SystemC, Verilog and C/C++; debug regressions, analyze coverage, and participate in code reviews. BS/MS in engineering or CS required. This role is not eligible for visa sponsorship.
System Verilog, UVM, SystemC, Verilog, C, C++, Linux, Windows, VIP
1mo
Save
Mark Applied
Hide
ASIC Design Verification Engineer (Santa Clara, CA)
Santa Clara or Austin
$127k-$190k/yr OnsiteFull Time
3+ YOE3+ years DV experience using UVM/assertion-based verification; experience verifying SoC/subsystems, caches, DDR, memory VIPs, DDR PHY, formal verification, PASIM, C++ and Python exposure; bachelor's/master's/PhD in science or engineering.
UVM, SystemVerilog, C++, Python, PASIM, UPF
4w
Save
Mark Applied
Hide
Sr. ASIC Design Verification Engineer (Silicon Engineering)
Austin, Texas, United States
OnsiteFull Time
5+ YOEBachelor's in EE/CE,5+ years design verification experience, proficiency with verification methodologies (UVM/OVM/VMM), scripting (Python), strong OOP and constrained-random verification skills.
UVM, OVM, VMM, Python
1mo
Save
Mark Applied
Hide
ASIC Engineer, Annapurna Labs
Austin, Texas, United States
OnsiteFull Time
Bachelor's in Electrical Engineering (required); design and verification experience for ASICs/SoCs; strong SystemVerilog skills; experience debugging architectures and verifying IP-to-system levels; familiarity with microarchitecture, synthesis, timing, and RTL development.
SystemVerilog, Python, Perl, ARM
2mo
Save
Mark Applied
Hide
Digital Design Verification Engineer
Bristol or Austin
£125k/yr OnsiteFull Time
5+ YOE5+ years in digital verification for high-performance ASICs/SoCs; strong SystemVerilog, SVA, UVM, Cocotb, formal verification, CDC/RDC, and algorithm modelling (MATLAB/Simulink or Python/NumPy) skills; experience with high-speed IP (SerDes, DDR/HBM, PCIe).
SystemVerilog, UVM, SVA, CocoTB, MATLAB/Simulink, Python, NumPy, Jasper, FPGA, RTL simulation, formal verification, linting, CDC/RDC, STA, UPF, CPF, gate-level simulation
1mo
Save
Mark Applied
Hide
Senior ASIC Design Engineer - Terawave
San Diego or California or Austin or Kent or Texas or Washington
$230k-$323k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
8+ YOEBS/MS in Electrical Engineering (or related), 8+ years experience in pre- and post-silicon SoC verification, strong SystemVerilog and DSP knowledge, emulation/FPGA/silicon bring-up experience, and verification methodology expertise.
SystemVerilog, MATLAB, SystemC, C, FPGA
2mo
Save
Mark Applied
Hide
Staff Design Verification Engineer – Coherent Interconnect
Boston or Austin
OnsiteFull Time
7+ YOELead verification for cache-coherent interconnect; 7+ years ASIC/SoC verification; SystemVerilog/UVM expertise; strong debugging and collaboration skills.
SystemVerilog, UVM, Verilog, Python
1mo
Save
Mark Applied
Hide
Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
San Diego or Nashua or Austin or Totowa or California or New Hampshire or Texas or New Jersey or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree with 8+ years (or equivalent experience); eligible for Secret clearance; experience with SystemVerilog/UVM/OVM and/or VHDL, Mentor Questa or Cadence tools; FPGA/ASIC verification, test plan development, and strong communication.
SystemVerilog, UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, Matlab, Simulink
1w
Save
Mark Applied
Hide
EDA Tools SW Engineer
Hillsboro or Santa Clara or Austin or Phoenix
$174k-$330k/yr HybridFull Time
6+ YOEBS+10/ MS+8/ PhD+6 in Electrical/Computer Engineering or related,6+ years relevant experience, technical leadership, foundry/process/ASIC physical design and verification knowledge.
1mo
Save
Mark Applied
Hide
Principal Applications Engineer
Austin, Texas, United States
$160k-$240k/yr RemoteFull Time
Extensive emulation platform experience, strong HDL and verification methodology knowledge (Verilog/SystemVerilog/VHDL, UVM/OVM), SoC/ASIC architecture expertise, scripting (Python/Perl/TCL), customer engagement and mentoring skills.
SynopsysZeBu, Mentor Veloce, Cadence Palladium, Verilog, SystemVerilog, VHDL, UVM, OVM, Python, Perl, TCL
1mo
Save
Mark Applied
Hide
DFT Engineer (CE-64000920)
Austin or Chandler or Greensboro
HybridFull Time
2+ YOEMSEE with 2+ years or BS with relevant experience; hands-on ASIC DFT design and verification; experience with FastScan, TestKompress, TetraMAX, Test Compiler; MBIST, scan/ATPG, Verilog/SystemVerilog/VHDL; scripting (Perl, Python, TCL); strong communication.
FastScan, TestKompress, TetraMAX, Test Compiler, Verilog, SystemVerilog, VHDL, Perl, Python, TCL
2w
Save
Mark Applied
Hide
R&D Engineer IC Design 4
Austin or San Jose
$122k-$195k/yr OnsiteFull Time
6+ YOEDesign and verify RTL/Verilog blocks for ASICs including synthesis, timing closure, formal verification, scripting, and RTL/gate-level power analysis. BS/MS in ECE and 6+ years experience.
Verilog, RTL, TCL, Perl, Synopsys Design Compiler, DC topo, Cadence RTL Compiler, Primetime, liberty (LIB), Synopsys Formality, Cadence Conformal, Spyglass, svn, git
1mo
Save
Mark Applied
Hide
Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
Explore Jobs
Expand Your Job Search
Top Cities Near Austin for Asic Verification Engineer
- Asic Verification Engineer jobs in Round Rock, TX
- Asic Verification Engineer jobs in New Braunfels, TX
- Asic Verification Engineer jobs in Cedar Park, TX
- Asic Verification Engineer jobs in Georgetown, TX
- Asic Verification Engineer jobs in San Marcos, TX
- Asic Verification Engineer jobs in Pflugerville, TX
- Asic Verification Engineer jobs in Leander, TX
- Asic Verification Engineer jobs in Kyle, TX
- Asic Verification Engineer jobs in Hutto, TX
- Asic Verification Engineer jobs in Taylor, TX
- Asic Verification Engineer jobs in Lakeway, TX
- Asic Verification Engineer jobs in Buda, TX
- Asic Verification Engineer jobs in Lockhart, TX
- Asic Verification Engineer jobs in Elgin, TX
- Asic Verification Engineer jobs in Bastrop, TX
- Asic Verification Engineer jobs in Manor, TX
- Asic Verification Engineer jobs in Lago Vista, TX
- Asic Verification Engineer jobs in Bee Cave, TX
- Asic Verification Engineer jobs in Marble Falls, TX
- Asic Verification Engineer jobs in Burnet, TX